CD54HC112, CD74HC112,
CD54HCT112, CD74HCT112
Data sheet acquired from Harris Semiconductor
SCHS141H
March 1998 - Revised October 2003
Dual J-K Flip-Flop with Set and Reset
Negative-Edge Trigger
Description
The ’HC112 and ’HCT112 utilize silicon-gate CMOS
technology to achieve operating speeds equivalent to LSTTL
parts. They exhibit the low power consumption of standard
CMOS integrated circuits, together with the ability to drive 10
LSTTL loads.
These flip-flops have independent J, K, Set, Reset, and
Clock inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Set and Reset
are accomplished asynchronously by low-level inputs.
The HCT logic family is functionally as well as pin-
compatible with the standard LS logic family.
.
Features
[ /Title
(CD74
HC112
,
CD74
HCT11
2)
/Sub-
ject
(Dual
J-K
Flip-
Flop
with
Set and
Reset
Nega-
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
• Asynchronous Set and Reset
• Complementary Outputs
• Buffered Inputs
• Typical f
MAX
= 60MHz at V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤
1µA at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC112F3A
CD54HCT112F3A
CD74HC112E
CD74HC112MT
CD74HC112M96
CD74HC112NSR
CD74HC112PW
CD74HC112PWR
CD74HC112PWT
CD74HCT112E
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld TSSOP
16 Ld PDIP
Pinout
CD54HC112, CD54HCT112 (CERDIP)
CD74HC112 (PDIP, SOIC, SOP, TSSOP)
CD74HCT112 (PDIP)
TOP VIEW
1CP 1
1K 2
1J 3
1S 4
1Q 5
1Q 6
2Q 7
GND 8
16 V
CC
15 1R
14 2R
13 2CP
12 2K
11 2J
10 2S
9 2Q
NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
©
2003, Texas Instruments Incorporated
1
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Functional Diagram
1S
1J
1K
1CP
1R
2S
2J
2K
2CP
2R
4
3
2
1
15
10
11
12
13
14
F/F 2
F/F 1
5
1Q
6
1Q
9
2Q
7
2Q
GND = 8
V
CC
= 16
TRUTH TABLE
INPUTS
S
L
H
L
H
H
H
H
H
R
H
L
L
H
H
H
H
H
CP
X
X
X
↓
↓
↓
↓
H
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
H
L
Toggle
No Change
Q
H
L
H (Note 1)
OUTPUTS
Q
L
H
H (Note 1)
No Change
L
H
H= High Level (Steady State)
L= Low Level (Steady State)
X= Don’t Care
↓
= High-to-Low Transition
NOTE:
1. Output states unpredictable if both S and R go High simultaneously after both being low at the same time.
2
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Absolute Maximum Ratings
DC Supply Voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For V
I
< -0.5V or V
I
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < V
O
< V
CC
+ 0.5V.
. . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, I
OK
For V
O
< -0.5V or V
O
> V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For V
O
> -0.5V or V
O
< V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . . . .±25mA
DC V
CC
or Ground Current, I
CC
. . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Information
Package Thermal Impedance,
θ
JA
(see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
o
C/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
o
C/W
D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
o
C/W
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108
o
C/W
Maximum Junction Temperature (Hermetic Package or Die) . 175
o
C
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150
o
C
Maximum Storage Temperature Range . . . . . . . . . .-65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300
o
C
Operating Conditions
Temperature Range, T
A
. . . . . . . . . . . . . . . . . . . . . . -55
o
C to 125
o
C
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, V
I
, V
O
. . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time, t
r
, t
f
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
HC TYPES
High Level Input
Voltage
V
IH
-
-
2
4.5
6
Low Level Input
Voltage
V
IL
-
-
2
4.5
6
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
I
I
V
CC
or
GND
V
OL
V
IH
or
V
IL
V
OH
V
IH
or
V
IL
-0.02
2
4.5
6
-
-4
-5.2
0.02
-
4.5
6
2
4.5
6
-
4
5.2
-
-
4.5
6
6
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.98
5.48
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.26
0.26
±0.1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.84
5.34
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.33
0.33
±1
1.5
3.15
4.2
-
-
-
1.9
4.4
5.9
-
3.7
5.2
-
-
-
-
-
-
-
-
-
-
0.5
1.35
1.8
-
-
-
-
-
-
0.1
0.1
0.1
-
0.4
0.4
±1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
SYMBOL
V
I
(V)
I
O
(mA) V
CC
(V)
MIN
25
o
C
TYP
MAX
-40
o
C TO 85
o
C
MIN
MAX
-55
o
C TO 125
o
C
MIN
MAX
UNITS
3
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
PARAMETER
Quiescent Device
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
3. For dual-supply systems theoretical worst case (V
I
= 2.4V, V
CC
= 5.5V) specification is 1.8mA.
I
I
V
CC
and
GND
V
CC
or
GND
V
CC
- 2.1
V
OL
V
IH
or
V
IL
V
IH
V
IL
V
OH
-
-
V
IH
or
V
IL
-
-
-0.02
4.5 to
5.5
4.5 to
5.5
4.5
2
-
4.4
-
-
-
-
0.8
-
2
-
4.4
-
0.8
-
2
-
4.4
-
0.8
-
V
V
V
SYMBOL
I
CC
V
I
(V)
V
CC
or
GND
I
O
(mA) V
CC
(V)
0
6
MIN
-
25
o
C
TYP
-
MAX
4
-40
o
C TO 85
o
C
MIN
-
MAX
40
-55
o
C TO 125
o
C
MIN
-
MAX
80
UNITS
µA
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4
4.5
4.5
-
-
-
-
0.1
0.26
-
-
0.1
0.33
-
-
0.1
0.4
V
V
-
5.5
-
±0.1
-
±1
-
±1
µA
I
CC
∆I
CC
(Note 3)
0
-
5.5
4.5 to
5.5
-
-
-
100
4
360
-
-
40
450
-
-
80
490
µA
µA
HCT Input Loading Table
INPUT
1S, 2S
1K, 2K
1R, 2R
1J, 2J, 1CP, 2CP
UNIT LOADS
0.5
0.6
0.65
1
NOTE: Unit Load is
∆I
CC
limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25
o
C.
Prerequisite For Switching Specifications
PARAMETER
HC TYPES
Pulse Width CP
t
W
-
2
4.5
6
80
16
14
-
-
-
-
-
-
100
20
17
-
-
-
120
24
20
-
-
-
ns
ns
ns
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
4
CD54HC112, CD74HC112, CD54HCT112, CD74HCT112
Prerequisite For Switching Specifications
PARAMETER
Pulse Width R, S
SYMBOL
t
W
(Continued)
V
CC
(V)
2
4.5
6
Setup Time J, K, to CP
t
SU
-
2
4.5
6
Hold Time J, K, to CP
t
H
-
2
4.5
6
Removal Time R to CP, S to CP
t
REM
-
2
4.5
6
CP Frequency
f
MAX
-
2
4.5
6
HCT TYPES
Pulse Width CP
Pulse Width R, S
Setup Time J, K, to CP
Hold Time J, K, to CP
Removal Time R to CP, S to CP
CP Frequency
t
SU
t
W
t
H
t
REM
t
W
f
MAX
-
-
-
-
-
-
4.5
4.5
4.5
4.5
4.5
4.5
16
18
16
3
20
30
-
-
-
-
-
-
-
-
-
-
-
-
20
23
20
3
25
25
-
-
-
-
-
-
24
27
24
3
30
20
-
-
-
-
-
-
ns
ns
ns
ns
ns
MHz
25
o
C
MIN
80
16
14
80
16
14
0
0
0
80
16
14
6
30
35
TYP
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
100
20
17
100
20
17
0
0
0
100
20
17
5
25
29
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
MIN
120
24
20
120
24
20
0
0
0
120
24
20
4
20
23
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
TEST
CONDITIONS
-
Switching Specifications
Input t
r
, t
f
= 6ns
PARAMETER
HC TYPES
Propagation Delay,
CP to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
Propagation Delay,
S to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
Propagation Delay,
R to Q, Q
t
PLH
, t
PHL
C
L
= 50pF
C
L
= 50pF
C
L
= 15pF
C
L
= 50pF
2
4.5
5
6
2
4.5
5
6
2
4.5
5
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
-
-
-
13
-
-
-
15
-
175
35
-
30
155
31
-
26
180
36
-
31
-
-
-
-
-
-
-
-
-
-
-
-
220
44
-
37
195
39
-
33
225
45
-
38
-
-
-
-
-
-
-
-
-
-
-
-
265
53
-
45
235
47
-
40
270
54
-
46
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
MIN
TYP
MAX
-40
o
C TO 85
o
C -55
o
C TO 125
o
C
MIN
MAX
MIN
MAX
UNITS
5
测试/测量
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
