74HC02; 74HCT02
Quad 2-input NOR gate
Rev. 03 — 18 September 2008
Product data sheet
1. General description
The 74HC02; 74HCT02 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC02; 74HCT02 provides a quad 2-input NOR function.
2. Features
I
Input levels:
N
For 74HC02: CMOS level
N
For 74HCT02: TTL level
I
ESD protection:
N
HBM JESD22-A114E exceeds 2000 V
N
MM JESD22-A115-A exceeds 200 V
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC02N
74HCT02N
74HC02D
74HCT02D
74HC02DB
74HCT02DB
74HC02PW
74HCT02PW
74HC02BQ
74HCT02BQ
−40 °C
to +125
°C
DHVQFN14
−40 °C
to +125
°C
TSSOP14
−40 °C
to +125
°C
SSOP14
−40 °C
to +125
°C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1
−40 °C
to +125
°C
Name
DIP14
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
Type number
plastic dual in-line compatible thermal enhanced very SOT762-1
thin quad flat package; no leads; 14 terminals;
body 2.5
×
3
×
0.85 mm
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
4. Functional diagram
2
1Y
1
3
5
2Y
4
6
8
9
4Y
13
11
12
mna216
2
3
5
6
8
9
11
12
1A
1B
2A
2B
3A
3B
4A
4B
≥1
1
≥1
4
3Y
10
≥1
10
A
Y
B
mna215
≥1
13
001aah084
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
terminal 1
index area
1A
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
001aac919
2
3
4
5
6
7
GND
3A
8
14 V
CC
13 4Y
12 4B
11 4A
10 3Y
9
3B
14 V
CC
13 4Y
12 4B
1B
2Y
2A
2B
GND
(1)
02
11 4A
10 3Y
9
8
3B
3A
1
1Y
02
001aac920
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y to 4Y
1A to 4A
1B to 4B
GND
V
CC
Pin description
Pin
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9,12
7
14
Description
data output
data input
data input
ground (0 V)
supply voltage
74HC_HCT02_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 18 September 2008
2 of 15
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care.
Function table
[1]
Output
nB
L
H
X
nY
H
L
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14, (T)SSOP14 and
DHVQFN14 packages
[1]
[2]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
−0.5
-
-
-
-
−50
−65
-
-
Max
+7
±20
±20
±25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
°C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
°C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
°C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
°C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
°C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
74HC_HCT02_3
Conditions
Min
2.0
0
0
−40
74HC02
Typ
5.0
-
-
-
Max
6.0
V
CC
V
CC
+125
Min
4.5
0
0
−40
74HCT02
Typ
5.0
-
-
-
Max
5.5
V
CC
V
CC
+125
Unit
V
V
V
°C
supply voltage
input voltage
output voltage
ambient temperature
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 18 September 2008
3 of 15
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
Table 5.
Recommended operating conditions
…continued
Voltages are referenced to GND (ground = 0 V)
…continued
Symbol Parameter
∆t/∆V
input transition rise and fall rate
Conditions
Min
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
-
-
-
74HC02
Typ
-
1.67
-
Max
625
139
83
Min
-
-
-
74HCT02
Typ
-
1.67
-
Max
-
139
-
ns/V
ns/V
ns/V
Unit
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC02
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 µA;
V
CC
= 2.0 V
I
O
=
−20 µA;
V
CC
= 4.5 V
I
O
=
−20 µA;
V
CC
= 6.0 V
I
O
=
−4.0
mA; V
CC
= 4.5 V
I
O
=
−5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 20
µA;
V
CC
= 2.0 V
I
O
= 20
µA;
V
CC
= 4.5 V
I
O
= 20
µA;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
supply current
input
capacitance
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
0.1
0.1
0.1
0.26
0.26
±0.1
2.0
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
±1
20
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
±1
40
-
V
V
V
V
V
µA
µA
pF
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
1.5
3.15
4.2
-
-
-
1.2
2.4
3.2
0.8
2.1
2.8
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
1.5
3.15
4.2
-
-
-
-
-
-
0.5
1.35
1.8
V
V
V
V
V
V
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
74HC_HCT02_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 18 September 2008
4 of 15
NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
Table 6.
Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HCT02
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
=
−20 µA
I
O
=
−4.0
mA
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
I
O
= 20
µA;
V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
∆I
CC
input leakage
current
supply current
additional
supply current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
per input pin;
V
I
= V
CC
−
2.1 V; I
O
= 0 A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
-
-
-
-
-
0
0.15
-
-
150
0.1
0.26
±0.1
2.0
540
-
-
-
-
-
0.1
0.33
±1
20
675
-
-
-
-
-
0.1
0.4
±1
40
735
V
V
µA
µA
µA
4.4
3.98
4.5
4.32
-
-
4.4
3.84
-
-
4.4
3.7
-
-
V
V
2.0
-
1.6
1.2
-
0.8
2.0
-
-
0.8
2.0
-
-
0.8
V
V
Conditions
Min
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
C
I
input
capacitance
-
3.5
-
-
-
-
-
pF
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V;
C
L
= 50 pF;
for load circuit see
Figure 7.
Symbol Parameter
Conditions
Min
74HC02
t
pd
propagation delay nA, nB to nY; see
Figure 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V
t
t
transition time
see
Figure 6
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
C
PD
power dissipation
capacitance
per package; V
I
= GND to V
CC
[3]
[2]
[1]
25
°C
Typ
Max
−40 °C
to +125
°C
Unit
Max
(85
°C)
Max
(125
°C)
-
-
-
-
-
-
-
-
25
9
7
7
19
7
6
22
90
18
-
15
75
15
13
-
115
23
-
20
95
19
16
-
135
27
-
23
110
22
19
-
ns
ns
ns
ns
ns
ns
ns
pF
74HC_HCT02_3
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 — 18 September 2008
5 of 15
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