SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
D
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
™
Family
State-of-the-Art
EPIC-
ΙΙ
B
™
BiCMOS Design
Significantly Reduces Power Dissipation
UBT
™
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 5 V, T
A
= 25°C
High-Impedance State During Power Up
and Power Down
Flow-Through Architecture Optimizes PCB
Layout
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54ABT16500B . . . WD PACKAGE
SN74ABT16500B . . . DGG OR DL PACKAGE
(TOP VIEW)
description
These 18-bit universal bus transceivers combine
D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A data is stored in the latch/flip-flop on
the high-to-low transition of CLKAB. OEAB is
active-high. When OEAB is high, the outputs are
active. When OEAB is low, the outputs are in the
high-impedance state.
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-ΙΙB, and UBT are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
©
1997, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
description (continued)
When V
CC
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
CC
through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
The SN54ABT16500B is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16500B is characterized for operation from –40°C to 85°C.
FUNCTION TABLE†
INPUTS
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↓
↓
H
L
A
X
L
H
L
H
X
X
OUTPUT
B
Z
L
H
L
H
B0‡
B0§
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established
§ Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was low before LEAB went low
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
logic symbol
†
OEAB
CLKAB
LEAB
OEBA
CLKBA
LEBA
1
55
2
27
30
28
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
4
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
1
1
6D
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
54
B1
A1
3
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
logic diagram (positive logic)
OEAB
1
CLKAB
55
LEAB
2
LEBA
28
CLKBA
30
OEBA
27
A1
3
1D
C1
CLK
1D
C1
CLK
54
B1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, V
O
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, I
O
: SN54ABT16500B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16500B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ABT16500B, SN74ABT16500B
18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS057G – DECEMBER 1990 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABT16500B
MIN
VCC
VIH
VIL
VI
IOH
IOL
∆t/∆v
∆t/∆V
CC
TA
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
Operating free-air temperature
Outputs enabled
200
–55
125
0
4.5
2
0.8
VCC
–24
48
10
200
–40
85
0
MAX
5.5
SN74ABT16500B
MIN
4.5
2
0.8
VCC
–32
64
10
MAX
5.5
UNIT
V
V
V
V
mA
mA
ns/V
µs/V
°C
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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