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74ABT16373 16-Bit Transparent D-Type Latch with 3-STATE Outputs
March 1994
Revised May 2005
74ABT16373
16-Bit Transparent D-Type Latch with 3-STATE Outputs
General Description
The ABT16373 contains sixteen non-inverting latches with
3-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state.
Features
s
Separate control logic for each byte
s
16-bit version of the ABT373
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Guaranteed latch-up protection
Ordering Code:
Order Number
74ABT16373CSSC
74ABT16373CMTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
OE
n
LE
n
D
0
–D
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Data Inputs
Outputs
© 2005 Fairchild Semiconductor Corporation
DS011666
www.fairchildsemi.com
74ABT16373
Functional Description
The ABT16373 contains sixteen D-type latches with
3-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the D
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LE
n
is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The 3-
STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OE
n
is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Truth Tables
Inputs
LE
1
X
H
H
L
OE
1
H
L
L
L
Inputs
LE
2
X
H
H
L
OE
2
H
L
L
L
D
8
–D
15
X
L
H
X
D
0
–D
7
X
L
H
X
Outputs
O
0
–O
7
Z
L
H
(Previous)
Outputs
O
8
–O
15
Z
L
H
(Previous)
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Previous previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
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2
74ABT16373
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current: OE Pin
(Across Comm Operating Range)
Other Pins
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to
5.5V
0.5V to V
CC
350 mA
500 mA
10V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current Breakdown Test
Input LOW Current
Input Leakage Test
4.75
2.5
2.0
0.55
1
1
7
V
Min
2.0
0.8
Typ
Max
Units
V
V
V
Min
Min
Min
Max
Max
Max
0.0
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
V
IN
V
IN
V
IN
V
IN
V
IN
I
ID
1.2
18 mA
3 mA
32 mA
64 mA
2.7V (Note 3)
V
CC
7.0V
0.5V (Note 3)
0.0V
1.9
P
A
P
A
P
A
P
A
V
1
1
All Other Pins Grounded
I
OZH
I
OZL
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
(Note 3)
Note 3:
Guaranteed, but not tested.
Note 4:
For 8 bits toggling, I
CCD
0.8 mA/MHz.
10
P
A
P
A
mA
0
5.5V V
OUT
0
5.5V V
OUT
Max
Max
0.0
Max
Max
Max
V
OUT
V
OUT
V
OUT
2.7V; OE
0.5V; OE
0.0V
V
CC
2.0V
2.0V
10
100
275
50
100
2.0
62
2.0
2.5
2.5
2.5
P
A
P
A
mA
mA
mA
mA
mA
mA
mA/
5.5V; All Others GND
All Outputs HIGH
All Outputs LOW
OE
V
I
V
CC
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
V
CC
All Others at V
CC
or GND
Max
Enable Input V
I
Data Input V
I
All Others at V
CC
or GND
No Load
0.15
MHz
Max
Outputs Open, LE
OE
GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
3
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74ABT16373
AC Electrical Characteristics
(SOIC and SSOP Packages)
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Output Disable Time
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Output Enable Time
1.4
1.4
1.7
1.7
1.1
1.5
2.4
1.6
V
CC
C
L
25
q
C
5.0V
50 pF
Typ
Max
5.6
5.6
6.0
5.5
6.1
5.6
7.1
6.5
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
5.6
5.6
6.0
5.5
6.1
5.6
7.1
6.5
ns
ns
ns
ns
C
L
Units
Min
1.4
1.4
1.7
1.7
1.1
1.5
2.4
1.6
AC Operating Requirements
(SOIC and SSOP Packages)
T
A
Symbol
Parameter
Min
f
TOGGLE
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
Maximum Toggle Frequency
Setup Time, HIGH
or LOW D
n
to LE
Hold Time, HIGH
or LOW D
n
to LE
Pulse Width,
LE HIGH
1.5
1.5
1.0
1.0
3.0
V
CC
C
L
25
q
C
5.0V
50 pF
Typ
100
Max
T
A
V
CC
40
q
C to
85
q
C
4.5V to 5.5V
50 pF
Max
MHz
C
L
Units
Min
1.5
1.5
1.0
1.0
3.0
ns
ns
ns
Capacitance
Symbol
C
IN
C
OUT
(Note 5)
Parameter
Input Capacitance
Output Capacitance
Typ
5
11
1 MHz, per MIL-STD-883, Method 3012.
Units
pF
pF
V
CC
V
CC
0V
5.0V
Conditions
(T
A
25
q
C)
Note 5:
C
OUT
is measured at frequency f
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