The ABT16245 contains sixteen non-inverting bidirectional
buffers with 3-STATE outputs. The device is byte controlled
with each byte functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.
www.fairchildsemi.com
2
74ABT16245
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
Over Voltage Latchup (I/O)
twice the rated I
OL
(mA)
65
q
C to
150
q
C
55
q
C to
125
q
C
55
q
C to
150
q
C
0.5V to
7.0V
0.5V to
7.0V
30 mA to
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
40
q
C to
85
q
C
4.5V to
5.5V
0.5V to 5.5V
0.5V to V
CC
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
500 mA
10V
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
2.5
2.0
0.55
Min
2.0
0.8
Typ
Max
Units
V
V
V
V
V
V
Min
Min
Min
Min
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
I
IN
I
OH
I
OH
I
OL
1.2
18 mA (OE
n
, T/R
n
)
3 mA (A
n
, B
n
)
32 mA (A
n
, B
n
)
64 mA (A
n
, B
n
)
I
IH
Input HIGH Current
1
1
P
A
P
A
P
A
P
A
V
Max
V
IN
V
IN
2.7V (OE
n
, T/R
n
) (Note 3)
V
CC
(OE
n
, T/R
n
)
7.0V (OE
n
, T/R
n
)
5.5V (A
n
, B
n
)
0.5V (OE
n
, T/R
n
) (Note 3)
0.0V (OE
n
, T/R
n
)
1.9
P
A (OE
n
, T/R
n
)
I
BVI
I
BVIT
I
IL
Input HIGH Current Breakdown Test
Input HIGH Current Breakdown Test (I/O)
Input LOW Current
7
100
Max
Max
Max
V
IN
V
IN
V
IN
V
IN
1
1
4.75
V
ID
Input Leakage Test
0.0
I
ID
All Other Pins Grounded
I
IH
I
OZH
Output Leakage Current
I
IL
I
OZL
Output Leakage Current
Output Short-Circuit Current
I
OS
I
CEX
I
ZZ
I
CCH
I
CCL
I
CCZ
I
CCT
Output HIGH Leakage Current
Bus Drainage Test
Power Supply Current
Power Supply Current
Power Supply Current
Additional I
CC
/Input
Outputs Enabled
Outputs 3-STATE
Outputs 3-STATE
I
CCD
Dynamic I
CC
(Note 3)
Note 3:
Guaranteed, but not tested.
10
P
A
P
A
mA
0
5.5V V
OUT
0
5.5V V
OUT
Max
V
OUT
Max
0.0
Max
Max
Max
V
OUT
V
OUT
2.7V (A
n
, B
n
); OE
0.5V (A
n
, B
n
); OE
0.0V (A
n
, B
n
)
V
CC
(A
n
, B
n
)
5.50V (A
n
, B
n
);
2.0V
2.0V
10
100
275
50
100
100
60
100
2.5
2.5
50
P
A
P
A
P
A
mA
All Others GND
All Outputs HIGH
All Outputs LOW
OE
n
V
I
Max
V
CC
, T/R
n
V
CC
2.1V
V
CC
2.1V
V
CC
2.1V
GND or V
CC
P
A
mA
mA
All others at V
CC
or GND
OE
n
, T/ R
n
V
I
Data Input V
I
Max
Outputs OPEN
OE
n
GND, T/R
n
GND or V
CC
One Bit Toggling, 50% Duty Cycle
P
A
mA/
All others at V
CC
or GND
No Load
0.1
MHz
3
www.fairchildsemi.com
74ABT16245
DC Extended Electrical Characteristics
Symbol
V
OLP
V
OLV
V
OHV
V
IHD
V
ILD
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Min
Typ
0.5
Max
0.9
Units
V
V
V
V
0.8
V
V
CC
5.0
5.0
5.0
5.0
5.0
Conditions
C
L
T
A
T
A
T
A
T
A
T
A
50 pF; R
L
500
:
25
q
C (Note 4)
25
q
C (Note 4)
25
q
C (Note 5)
25
q
C (Note 5)
25
q
C (Note 6)
1.4
2.5
2.0
1.0
3.0
1.4
1.2
Note 4:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 6:
Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
T
A
Symbol
Parameter
Min
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation
Delay Data to Outputs
Output Enable
Time
Output Disable
Time
1.0
1.0
1.5
1.5
1.3
1.3
V
CC
C
L
25
q
C
5V
50 pF
Typ
2.4
2.8
3.6
3.7
4.6
3.7
Max
3.9
3.9
6.3
6.3
6.9
6.9
T
A
55
q
C to
125
q
C
4.5V – 5.5V
50 pF
Max
4.5
5.2
6.4
6.9
6.9
6.9
C
L
T
A
40
q
C to
85
q
C
4.5V – 5.5V
50 pF
Max
3.9
3.9
6.3
6.3
6.9
6.9
ns
ns
ns
C
L
Units
V
CC
V
CC
Min
0.5
0.5
0.8
0.9
1.3
1.0
Min
1.0
1.0
1.5
1.5
1.3
1.3
Extended AC Electrical Characteristics
T
A
40
q
C to
85
q
C
V
CC
Symbol
Parameter
C
L
4.5V–5.5V
50 pF
T
A
40
q
C to
85
q
C
4.5V–5.5V
250 pF
C
L
T
A
40
q
C to
85
q
C
4.5V–5.5V
250 pF
Units
C
L
V
CC
V
CC
16 Outputs Switching
(Note 7)
Min
f
TOGGLE
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Time
Maximum Toggle Frequency
Propagation Delay
Data to Outputs
Output Enable
Time
Output Disable
1.5
1.5
1.5
1.5
1.0
1.0
Typ
100
5.0
5.3
6.5
6.5
6.9
6.9
Max
1 Output Switching
(Note 8)
Min
1.5
1.5
2.5
2.5
(Note 10)
Max
6.0
6.0
8.2
8.2
16 Outputs Switching
(Note 9)
Min
2.5
2.5
2.5
2.5
(Note 10)
Max
MHz
8.0
8.0
10.0
9.0
ns
ns
ns
Note 7:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8:
This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 9:
This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10:
3-STATE delay are dominated by the RC network (500
:
, 250 pF) on the output and have been excluded from the datasheet.
www.fairchildsemi.com
4
74ABT16245
Skew
T
A
40
q
C to
85
q
C
4.5V–5.5V
50 pF
C
L
T
A
40
q
C to
85
q
C
4.5V–5.5V
250 pF
Units
C
L
V
CC
Symbol
Parameter
V
CC
16 Outputs Switching
(Note 11)
Max
t
OSHL
(Note 13)
t
OSLH
(Note 13)
t
PS
(Note 14)
t
OST
(Note 13)
t
PV
(Note 15)
Pin to Pin Skew
HL Transitions
Pin to Pin Skew
LH Transitions
Duty Cycle
LH–HL Skew
Pin to Pin Skew
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
1.3
1.3
1.5
1.7
2.0
16 Outputs Switching
(Note 12)
Max
1.5
1.5
2.0
2.5
3.0
ns
ns
ns
ns
ns
Note 11:
This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 12:
These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13:
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW to HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (t
OST
). The specification is guaranteed but not tested.
Note 14:
This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 15:
Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
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