®
All new designs should use XC3000A.
Information on XC3000 is presented here
as a reference for existing designs.
XC3000 bitstreams are upward compatible
to XC3000A without modification.
IMPORTANT NOTICE
XC3000
Logic Cell Array Family
Product Specification
Features
Description
XC3000 is the original family of devices in the XC3000
class of Field Programmable Gate Array (FPGA) architec-
tures. The XC3000 family has a proven track record in
addressing a wide range of design applications, including
general logic replacement and sub-systems integration.
For a thorough description of the XC3000 architecture see
the preceding pages of this data book.
The XC3000 Family covers a range of nominal device
densities from 2,000 to 9,000 gates, practically achievable
densities from 1,000 to 6,000 gates. Device speeds,
described in terms of maximum guaranteed toggle fre-
quencies, range from 70 to 125 MHz. The performance of
a completed design depends upon placement and routing
implementation, so, like with any gate array, the final
verification of device utilization and performance can only
be known after the design has been placed and routed.
•
Industry-leading FPGA family with five device types
– Logic densities from 1,000 to 6,000 gates
– Up to 144 user-definable I/Os
•
Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns
logic delays
•
Advanced CMOS static memory technology
– Low quiescent and active power consumption
•
XC3000-specific features
– Ultra-low current option in Power-Down mode
– 4-mA output sink and source current
– Broad range of package options includes plastic and
ceramic quad flat packs, plastic leaded chip carriers
and pin grid arrays
– 100% bitstream compatible with the XC3100 family
– Commercial, industrial, military, “high rel”, and MIL-
STD-883 Class B grade devices
– Easy migration to XC3300 series of HardWire mask-
programmed devices for high-volume production
Device
XC3020
XC3030
XC3042
XC3064
XC3090
CLBs
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
User I/Os
Max
64
80
96
120
144
Flip-Flops
256
360
480
688
928
Horizontal
Longlines
16
20
24
32
40
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
2-153
XC3000 Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
V
CC
V
IN
V
TS
T
STG
T
SOL
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
Junction temperature plastic
T
J
Junction temperature ceramic
+150
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
–65 to +150
+260
+125
Units
V
V
V
°C
°C
°C
°C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
V
CC
Description
Supply voltage relative to GND Commercial 0°C to +85°C junction
Supply voltage relative to GND Industrial -40°C to +100°C junction
V
IHT
V
ILT
V
IHC
V
ILC
T
IN
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
High-level input voltage — CMOS configuration
Low-level input voltage — CMOS configuration
Input signal transition time
Min
4.75
4.5
2.0
0
70%
0
Max
5.25
5.5
V
CC
0.8
100%
20%
250
Units
V
V
V
V
V
CC
V
CC
ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°C.
2-154
DC Characteristics Over Operating Conditions
Symbol
V
OH
V
OL
V
OH
V
OL
V
CCPD
I
CCPD
Description
High-level output voltage (@ I
OH
= –4.0 mA, V
CC
min)
Commercial
Low-level output voltage (@ I
OL
= 4.0 mA, V
CC
min)
High-level output voltage (@ I
OH
= –4.0 mA, V
CC
min
)
Industrial
Low-level output voltage (@ I
OL
= 4.0 mA, V
CC
min
)
Power-down supply voltage (PWRDWN must be Low)
Power-down supply current (V
CC(MAX)
@ T
MAX
)
1
XC3020
XC3030
XC3042
XC3064
XC3090
I
CCO
Quiescent LCA supply current in addition to I
CCPD2
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
I
IL
C
IN
Input Leakage Current
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
I
RIN
I
RLL
Pad pull-up (when selected) @ V
IN
= 0 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
0.02
–10
2.30
50
80
120
170
250
0.40
V
V
µA
µA
µA
µA
µA
µA
mA
µA
3.76
0.40
V
V
Min
3.86
Max
Units
V
500
10
+10
10
15
pF
pF
15
20
0.17
3.4
pF
pF
mA
mA
Note: 1. Devices with much lower I
CCPD
tested and guaranteed at V
CC
= 3.2 V, T = 25°C can be ordered with a
Special Product Code.
XC3020 SPC0107: I
CCPD
= 1
µA
XC3030 SPC0107: I
CCPD
= 2
µA
XC3042 SPC0107: I
CCPD
= 3
µA
XC3064 SPC0107: I
CCPD
= 4
µA
XC3090 SPC0107: I
CCPD
= 5
µA
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
CC
or GND,
and the LCA configured with a MakeBits tie option.
2-155
XC3000 Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB Output (X, Y)
(Combinatorial)
1 T
ILO
CLB Input
(A,B,C,D,E)
2 T
ICK
CLB Clock
12 T
CL
4 T
DICK
CLB Input
(Direct In)
6 T
ECCK
CLB Input
(Enable Clock)
8 T
CKO
CLB Output
(Flip-Flop)
7 T
CKEC
11 T
CH
5 T
CKDI
3 T
CKI
CLB Input
(Reset Direct)
13 T
RPW
9 T
RIO
CLB Output
(Flip-Flop)
X5388
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
Description
Global and Alternate Clock Distribution*
Either:
Normal
IOB input pad through clock buffer
to any CLB or IOB clock input
Or:
Fast
(CMOS only) input pad through clock
buffer to any CLB or IOB clock input
TBUF
driving a Horizontal Longline (L.L.)*
I to L.L. while T is Low (buffer active)
T↓ to L.L. active and valid with single pull-up resistor
T↓ to L.L. active and valid with pair of pull-up resistors
T↑ to L.L. High with single pull-up resistor
T↑ to L.L. High with pair of pull-up resistors
BIDI
Bidirectional buffer delay
Symbol
-70
Max
-100
Max
-125
Max
Units
T
PID
T
PIDC
8.0
6.5
7.5
6.0
7.0
5.7
ns
ns
T
IO
T
ON
T
ON
T
PUS
T
PUF
5.0
11.0
12.0
24.0
17.0
4.7
10.0
11.0
22.0
15.0
4.5
9.0
10.0
17.0
12.0
ns
ns
ns
ns
ns
T
BIDI
2.0
1.8
1.7
ns
* Timing is based on the XC3042, for other devices see XACT timing calculator.
2-156
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
Set-up time before clock K
Logic Variables
A, B, C, D, E
Data In
DI
Enable Clock
EC
Reset Direct inactive RD
Hold Time after clock K
Logic Variables
Data In
Enable Clock
Symbol
-70
Min Max
-100
Min
Max
-125
Min
Max Units
1 T
ILO
9.0
7.0
5.5
ns
8 T
CKO
T
QLO
6.0
13.0
5.0
10.0
4.5
8.0
ns
ns
2 T
ICK
4 T
DICK
6 T
ECCK
8.0
5.0
7.0
1.0
7.0
4.0
5.0
1.0
5.5
3.0
4.5
1.0
ns
ns
ns
ns
A, B, C, D, E
DI
EC
3 T
CKI
5 T
CKDI
7 T
CKEC
0
4.0
0
0
2.0
0
0
1.5
0
ns
ns
ns
Clock
Clock High time
Clock Low time
Max flip-flop toggle rate
Reset Direct (RD)
RD width
delay from rd to outputs X or Y
Global Reset (RESET Pad)*
RESET width (Low)
delay from RESET pad to outputs X or Y
11 T
CH
12 T
CL
F
CLK
5.0
5.0
70
4.0
4.0
100
3.0
3.0
125
ns
ns
MHz
13 T
RPW
9 T
RIO
8.0
8.0
7.0
7.0
6.0
6.0
ns
ns
T
MRW
T
MRQ
25.0
23.0
21.0
19.0
20.0
17.0
ns
ns
*Timing is based on the XC3042, for other devices see XACT timing calculator.
Note: The CLB K to Q output delay (T
CKO
, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (T
CKDI
, #5) of any CLB on the same die.
2-157
淘e淘
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
