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74F825 8-Bit D-Type Flip-Flop
April 1988
Revised October 2000
74F825
8-Bit D-Type Flip-Flop
General Description
The 74F825 is an 8-bit buffered register. It has Clock
Enable and Clear features which are ideal for parity bus
interfacing in high performance microprogramming sys-
tems. Also included in the 74F825 are multiple enables that
allow multi-user control of the interface.
Features
s
3-STATE output
s
Clock enable and clear
s
Multiple output enables
Ordering Code:
Order Number
74F825SC
74F825SPC
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009597
www.fairchildsemi.com
74F825
Unit Loading/Fan Out
U.L.
Pin Names
D
0
–D
7
O
0
–O
7
OE
1
, OE
2
, OE
3
EN
CLR
CP
Description
HIGH/LOW
Data Inputs
3-STATE Data Outputs
Output Enable Input
Clock Enable
Clear
Clock Input
1.0/1.0
150/40 (33.3)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
Input I
IH
/I
IL
Output I
OH
/I
OL
20
µ
A/
−
0.6 mA
−
3 mA/24 mA (20 mA)
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
0.6 mA
20
µ
A/
−
1.2 mA
Functional Description
The 74F825 consists of eight D-type edge-triggered
flip-flops. This device has 3-STATE true outputs and is
organized in broadside pinning. In addition to the clock and
output enable pins, the buffered clock (CP) and buffered
Output Enable (OE) are common to all flip-flops. The
flip-flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the
LOW-to-HIGH CP transition. With the OE LOW the con-
tents of the flip-flops are available at the outputs. When the
OE is HIGH, the outputs go to the high impedance state.
Operation of the OE input does not affect the state of the
flip-flops. The 74F825 has Clear (CLR) and Clock Enable
(EN) pins.
When the CLR is LOW and the OE is LOW the outputs are
LOW. When CLR is HIGH, data can be entered into the
flip-flops. When EN is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN is HIGH the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
Inputs
OE CLR EN CP D
H
H
H
L
H
L
H
H
L
L
L
L
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
X
X
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
L
H
L
H
X
X
Internal Output
Function
Q
NC
NC
NC
NC
H
H
H
L
H
L
NC
NC
O
Z
Z
Z
NC
Z
L
Z
Z
L
H
NC
NC
Hold
Hold
Hold
Hold
Clear
Clear
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
X
H
L
L
=
LOW Voltage Level
H
=
HIGH Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74F825
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
3-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
−
65
°
C to
+
150
°
C
−
55
°
C to
+
125
°
C
−
55
°
C to
+
150
°
C
−
0.5V to
+
7.0V
−
0.5V to
+
7.0V
−
30 mA to
+
5.0 mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
0
°
C to
+
70
°
C
+
4.5V to
+
5.5V
−
0.5V to V
CC
−
0.5V to
+
5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
Voltage
10% V
CC
10% V
CC
5% V
CC
5% V
CC
V
OL
I
IH
I
BVI
I
CEX
V
ID
I
OD
I
IL
I
OZH
I
OZL
I
OS
I
ZZ
I
CCZ
Output LOW Voltage
Input HIGH
Current
Input HIGH Current
Breakdown Test
Output HIGH
Leakage Current
Input Leakage
Test
Output Leakage
Circuit Current
Input LOW Current
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Buss Drainage Test
Power Supply Current
75
−60
4.75
3.75
−0.6
50
−50
−150
500
90
10% V
CC
2.5
2.4
2.7
2.7
0.5
5.0
7.0
50
V
µA
µA
µA
V
µA
mA
µA
µA
mA
µA
mA
Min
Max
Max
Max
0.0
0.0
Max
Max
Max
Max
0.0V
Max
V
Min
Min
2.0
0.8
−1.2
Typ
Max
Units
V
V
V
Min
V
CC
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
I
IN
= −18
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OH
= −1
mA
I
OH
= −3
mA
I
OL
=
24 mA
V
IN
=
2.7V
V
IN
=
7.0V
V
OUT
=
V
CC
I
ID
=
1.9
µA
All Other Pins Grounded
V
IOD
=
150 mV
All Other Pins Grounded
V
IN
=
0.5V
V
OUT
=
2.7V
V
OUT
=
0.5V
V
OUT
=
0V
V
OUT
=
5.25V
V
O
=
HIGH Z
3
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74F825
AC Electrical Characteristics
T
A
= +25°C
Symbol
Parameter
Min
f
MAX
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum Clock Frequency
Propagation Delay
CP to O
n
Propagation Delay
CLR to O
n
Output Enable Time
OE to O
n
Output Disable TIme
OE to O
n
100
2.0
2.0
4.0
2.0
2.0
1.5
1.5
V
CC
= +5.0V
C
L
=
50 pF
Typ
160
6.5
6.6
7.4
6.5
6.6
3.5
3.3
9.5
9.5
12.0
10.5
10.5
7.0
7.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
C
L
=
50 pF
Min
60
2.0
2.0
4.0
2.0
2.0
1.0
1.0
10.5
10.5
13.0
13.0
13.0
7.5
7.5
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
C
L
=
50 pF
Min
70
2.0
2.0
4.0
2.0
2.0
1.5
1.5
10.5
10.5
13.0
11.5
11.5
7.5
7.5
ns
Max
MHz
ns
ns
Units
AC Operating Requirements
T
A
= +25°C
Symbol
Parameter
V
CC
= +5.0V
Min
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
S
(H)
t
S
(L)
t
H
(H)
t
H
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
REC
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
Setup Time, HIGH or LOW
EN to CP
Hold Time, HIGH or LOW
EN to CP
CP Pulse Width
HIGH or LOW
CLR Pulse Width, LOW
CLR Recovery Time
2.5
2.5
2.5
2.5
4.5
2.5
2.0
0
5.0
5.0
5.0
5.0
Max
T
A
= −55°C
to
+125°C
V
CC
= +5.0V
Min
4.0
4.0
2.5
2.5
5.0
3.0
3.0
2.0
6.0
6.0
5.0
5.0
Max
T
A
=
0°C to
+70°C
V
CC
= +5.0V
Min
3.0
3.0
2.5
2.5
5.0
3.0
1.0
0
6.0
6.0
5.0
5.0
ns
ns
ns
ns
ns
Max
Units
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