Preliminary
OCX256L • OCX256P Crosspoint Switch with LVDS (Preliminary) • Crosspoint Switch with LVPECL (Preliminary)
June 2002
Revised March 2003
OCX256L • OCX256P
Crosspoint Switch with LVDS (Preliminary) •
Crosspoint Switch with LVPECL (Preliminary)
General Description
The OCX256 SRAM-based devices are non-blocking 128
X 128 digital crosspoint switches and are available in LVDS
(Low Voltage Differential Signaling) and LVPECL (Low
Voltage PECL) versions. Both devices are capable of data
rates of 667 Megabits per second per port. The I/O ports
are fixed as either input or output ports. The input ports
support flow-through mode only. The output ports are indi-
vidually programmable to operate in either flow-through
(asynchronous) or registered (synchronous) mode. Each
output register may be clocked by a global clock or a next
neighbor clock source.
The patented ActiveArray provides greater density, supe-
rior performance, and greater flexibility compared to a tra-
ditional n:1 multiplexer architecture. The OCX devices
support various operating modes covering one input to one
output at a time as well as one input to many outputs, plus
a special broadcast mode to program one input to all out-
puts while maintaining maximum data rates. In all modes
data integrity and connections are maintained on all
unchanged data paths.
The RapidConfigure
parallel interface allows fast configu-
ration of both the Output Buffers and the switch matrix.
Readback is supported for device test and verification pur-
poses. The OCX256 also supports the industry standard
JTAG (IEEE 1149.1) interface for boundary scan testing.
The JTAG interface can also be used to download configu-
ration data to the device and readback data. A functional
block diagram of the OCX256 is shown in Figure 1.
s
256 configurable I/O ports
128 dedicated differential input ports
128 dedicated differential output ports
LVTTL control interface
Output Enable control for all outputs
s
Non-blocking switch matrix
Patented ActiveArray
matrix for superior performance
Double-buffered configuration RAM cells for
simultaneous global updates
ImpliedDisconnect
function for single cycle
disconnect/connect
s
Full Broadcast and multicast capability
One-to-One and One-to-Many connections
Special broadcast mode routes one input to all outputs
at maximum data rate
s
Registered and flow-through data modes
333 MHz synchronous mode
667 Mb/s asynchronous mode
Low jitter and signal skew
Low duty cycle distortion
s
RapidConfigure parallel interface for
configuration and readback
s
JTAG serial interface for configuration and Boundary
Scan testing
s
792 TBGA package with 1.00mm ball spacing
s
Integrated Termination Resistors
Features
s
667 Mb/s port data bandwidth, >85Gb/s aggregate
bandwidth
s
Low power CMOS, 2.5V and 3.3V power supply
s
SRAM-based, in-system programmable
s
LVDS I/O (OCX256L) and LVPECL I/O (OCX256P)
versions
Applications
• SONET/SDH and DWDM
• Digital Cross-Connects
• System Backplanes and Interconnects
• High Speed Test Equipment
• ATM Switch Cores
• Video Switching
Ordering Code:
Order Number
OCX256LTB792
OCX256PTB792
Package Number
BGA792A
BGA792A
Package Description
792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch,
40mm Square
792-Ball Thermally-Enhanced Ball Grid Array (TBGA), JEDEC MO-149, 1.0mm pitch,
40mm Square
ActiveArray, ImpliedDisconnect, and RapidConfigure are trademarks of Fairchild Semiconductor Corporation.
© 2003 Fairchild Semiconductor Corporation
DS500749
www.fairchildsemi.com
Preliminary
OCX256L • OCX256P
256
IN[127:0]
Input
Buffers
128 x 128
Crosspoint
Switch Matrix
256
OUT[127:0]
Output
Buffers
2 CLK
OE
RapidConfigure
Signals
RCA[6:0] 7
RCB[6:0] 7
RCI[3:0] 4
RCO[4:0] 5
RC_CLK
RC_EN
UPDATE
Configuration and
Programming Logic
TCK
TMS
TDI
TRST
TDO
HW_RST
JTAG
Signals
FIGURE 1. OCX256 Functional Block Diagram
Introduction
The OCX256 is a differential crosspoint-switching device.
The main functional block of the device is a Switch Matrix
as shown in Figure 1. The Switch Matrix is a x-y structure
supporting an input-to-output data flow. Figure 2 shows a
conceptual view of the switch matrix with inputs connected
to the horizontal trace and outputs to the vertical trace.
Connections between vertical and horizontal lines are
implemented with a proprietary high-performance buffering
circuit. Signal path delays through the Switch Matrix are
very well balanced, resulting in predictable and uniform
pin-to-pin delays.
Note:
For the purpose of clarity, the logic diagrams within this datasheet
are conceptual representations only and do not show actual circuit imple-
mentation.
Data
Loading
SRAM
Cell
Active
SRAM
Cell
UPDATE
Proprietary High-performance
Buffering Circuit
FIGURE 2. OCX256 Switch Matrix
The Active SRAM cells are responsible for establishing
connections in the switch matrix by turning on the intercon-
nect circuit, while the Loading SRAM cell can be used to
store a second configuration that can be transferred to the
Active SRAM cell at a later time. The two SRAM cells are
arranged so that a double buffered scheme can be
employed. Through the use of an internal signal (generated
automatically during a programming cycle) it is possible to
store a second configuration map in the Loading SRAM
while the Active SRAM maintains its present connection
status. When the UPDATE signal is asserted LOW (Active
LOW), the contents of the Loading SRAM cell are trans-
ferred to the Active SRAM cell and the switch matrix con-
nection is either made or broken.
The UPDATE signal can be used to control when the
switch matrix is reconfigured. For instance, as long as the
UPDATE signal is de-asserted (held HIGH), the Loading
SRAM cells for the entire switch matrix could be changed
without affecting the current configuration of the switch.
When the UPDATE signal is asserted LOW, the entire
switch matrix would be reconfigured simultaneously. If the
UPDATE signal is asserted continuously, all crosspoint pro-
gramming commands (generated by RapidConfigure or
JTAG programming cycles) will take effect immediately,
since the Loading SRAM cell’s contents will be transferred
directly to the Active SRAM cell.
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2
Preliminary
OCX256L • OCX256P
Introduction
(Continued)
Input and Output Buffers
All of the input buffers are differential inputs with flow-
through mode. The output buffers are programmable for
either flow-through or registered mode. Figure 3 shows the
basic block diagram of the input and output blocks with the
sources for the output control signals (OE and CLK). The
control signals are explained in more details in the follow-
ing sections
Output Mode
Select
Input
Switch
Matrix
Output
D
Q
CLK
Next
Neighbor
Clock
Select
OE
FIGURE 3. Input and Output Buffer Configuration
Input and Output Port Function Mode
The following legend describes the various modes of the
Input and Output Ports and the specification used by the
OCXPro Software.
Legend:
Ax–Switch Matrix Signal
Px–Port Signal
OE–Output Enable (Active LOW)
CLK–Clock
TABLE 1. Summary for Programmable I/O Attributes for OCX256
Symbol
Input
Px
Ax
I/O Port Function
The external signal is buffered from the Input Port pin to the
corresponding Switch Matrix line.
Mnemonic
IN
Output
Ax
Px
The internal signal is buffered from the corresponding Switch
Matrix line to the Output Port pin. In this mode an optional
output enable (OE) can be selected. The default state is logic
high with enable set to ON.
OP
OE
Ax
CLK
D
Q
Px
Registered Output The internal signal on the Switch Matrix line is registered by
an edge-triggered register within the Output Port. A clock
source is required in this mode. An output enable (OE) is
available but not required.
No Connect
In this mode, the output Port pin is isolated from the Switch
Matrix
Output Control Signals
RO
OE
NC
Px
Ax
Broadcast Mode
The OCX256 has a special Broadcast Mode which con-
nects any input to all outputs without performance degra-
dation. The input is selected using RapidConfigure or
JTAG and disconnects all other inputs. The Global Update
pin (UPDATE) must be held high during Broadcast Mode.
Asserting the UPDATE pin returns the array to the previous
program condition.
Output Buffer Configuration
Every output port of the OCX256 can be configured as
either a flow-through or registered output. In registered
mode there are two clock sources that are available:
• Global Clock
• Next Neighbor
Additionally, there are output control signals.
Every output port of the OCX has a global Output Enable
signal (OE). All output buffers have output enables that
have programmable polarity and are individually config-
urable.
Additionally each output can be permanently enabled
(always ON) or disabled (always OFF) which is useful for
applications which need to 3-STATE outputs (for example
when using multiple chips in expansion mode) or for power
saving in designs that do not need to use all the outputs
available.
Two control bits are used to control the function of the out-
put enable function as described in Table 5.
3
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Preliminary
OCX256L • OCX256P
Introduction
(Continued)
Neighboring Output Port as a Clock Source
A physically adjacent port can be used as a clock source
for an output port configured in registered mode. These
outputs are grouped in pairs such that the signal being
switched through OUT0 can be used to clock the signal
being switched through OUT1, and vice versa. Any single
clock or data input signal can be used to clock any other
input signal provided they are switched to an appropriate
output pair (see Table 2). Figure 4 shows the implementa-
tion of next neighbor output port clocking in the OCX256
switch.
For example, INx is used for data input while INy is used
for the corresponding clock. INx is connected to OUT0 via
the crosspoint array while INy is connected to OUT1 via the
crosspoint array. OUT0 is configured in registered output
(RO) mode with OUT1 as its next neighbor clock selection.
OUT1 will output the clock signal as well as clock the data
in OUT0. Adjacent port selection is required for next neigh-
bor clocking in the registered output mode.
This feature is useful in many applications where different
types of data switching through the crosspoint array have
various associated clocks. To match the delays in the data
and corresponding clocks, it is common practice to pass
the clocks through the switch along with the data.
Output Mode
Select
Crosspoint
Array
Any Input
Port
(INx)
D
CLK
Next
Neighbor
Clock
Select
Q
OUT0
OE
Output Mode
Select
Any Input
Port
(INy)
D
CLK
Next
Neighbor
Clock
Select
OE
Q
OUT1
FIGURE 4. Next Neighbor Clock Block Diagram
The advantages of next neighbor clocking are:
1. Using next neighbor clocking in the registered output
(RO) mode helps reduce the skew in outgoing data.
2. For a design with a large number of outputs switching
simultaneously, next neighbor clocking mode is useful
to stagger outputs for reduced board noise caused by
simultaneous switching outputs.
Note:
Selecting the next neighbor clock for both outputs at the same time is
not recommended. Only one output in the pair at a time can be clocked by
its next neighbor.
TABLE 2. Next Neighbor Outputs
Pairing Sequence for Neighboring Outputs
Output Next Neighbor Pairs 0,1 2,3 4,5 6,7 8,9
••••
124,125 126,127
Only OUT1 can neighbor with OUT0, OUT3 with OUT2, etc. OUT2 cannot neighbor with OUT1, or OUT4 with OUT3, etc.
RapidConfigure Interface
RapidConfigure (RC) is a 25 signal parallel interface that is
used to program the OCX256 device. The 25 pins are allo-
cated as follows:
RCA[6:0]
RCB[6:0]
RCI[3:0]
RapidConfigure Programming Instructions
The RC interface supports both write and read types of
operations:
1. Write Operations (reset crosspoint and Input or Output
Buffer (IOB), configure an Output Buffer, connect/dis-
connect crosspoint)
2. Read Operations (Output Buffer and crosspoint config-
uration read)
=
RapidConfigure Address A.
RCA are input pins.
=
RapidConfigure Address B.
RCB are input pins.
=
RapidConfigure Instruction Bits
RCO are output pins.
RCO[4:0]
=
RapidConfigure Readback.
RC_CLK
RC_EN
=
RapidConfigure Clock
=
RapidConfigure Cycle Enable
(state is sensed on negative edge of clock)
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4
Preliminary
OCX256L • OCX256P
Introduction
RCI[3:0]
0000
0001
0010
X
RCA[6:0]
(Continued)
TABLE 3. RapidConfigure Programming Instructions
RCB[6:0]
RCO[4:0]
Instruction
Reserved
Reserved
X
Reset
Crosspoint Array
Reset, along with an Update operation (UPDATE
pin or Update command), resets the entire cross-
point array to no connect. All Output Buffers
remain unchanged by this operation.
Connects the input selected by RCB[6:0] to all
output ports and disconnects all other inputs. The
Global Update (UPDATE) pin must be held high
during Broadcast mode. Activating the Global
Update pin returns the array to the previous pro-
gram condition.
Program an Output Buffer specified by RCA[6:0].
See Table 5 for RCB[6:0] bit assignment and
buffer functionality.
Description
0011
X
Input Port
Address
Set Array
to
Broadcast Mode
0100
Output Port
Address
Data
Configure
an
Output Buffer
0101
Cycle 1 Output Port Input Port
Address
Address
Cycle 2
X
X
X
Readback Crosspoint, This is a two-cycle instruction.
Output Buffer Status
Specify the crosspoint connect status at output
location specified by RCA[6:0] to the input location
specified by RCB[6:0].
Readback (using RCO[4:0]) the status of the out-
put buffer specified in Cycle 1 by RCA[6:0], the
output buffer specified in Cycle 1 by RCO[4:0] and
the crosspoint connect status.
See Table 4 for RCO[4:0] readback pin assign-
ment.
Update
Disconnect Input
Disconnect Input
and
Output
Program the Global Update function without the
use of the UPDATE pin.
Disconnect the crosspoint cells of the output row
location specified by RCA[6:0].
Disconnect the crosspoint cell at the output loca-
tion specified by RCA[6:0] to the input location
specified by RCB[6:0].
All other connections from the source input
address or to the same output address remain the
same as before.
Connect the crosspoint cell at the output location
specified by RCA[6:0] to the input location speci-
fied by RCB[6:0].
All other connections from the same input address
or to the same output address are set to No Con-
nect (NC).
Connect the crosspoint cell at the output location
specified by RCA[6:0] to the input location speci-
fied by RCB[6:0].
All other connections to the same output address
are set to No Connect while all other connections
from the same input address remain the same as
before.
Output Data
0110
0111
1000
X
X
X
Input Port
Address
Output Port Input Port
Address
Address
1001
Output Port Input Port
Address
Address
Connect,
with
ImpliedDisconnect
1010
Output Port Input Port
Address
Address
Connect,
without
ImpliedDisconnect
1011
1100
1101
X
X
Reserved
Reserved
Reset All
Reset the switch matrix to No Connects (NC).
Update is forced internally. Sets the Output Buffer
to Flow-through mode with Output Enabled.
1110
1111
X = Don’t care.
Reserved
Reserved
5
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