OCX256 Crosspoint Switch
Advanced Datasheet
Features
667 Mb/s port data bandwidth, >85Gb/s aggregate bandwidth
Low power CMOS, 2.5V and 3.3V power supply
SRAM-based, in-system programmable
LVDS I/O (OCX256L) and LVPECL I/O (OCX256P)
versions
•
256 configurable I/O ports
– 128 dedicated differential input ports
– 128 dedicated differential output ports
– LVTTL control interface
– Output Enable control for all outputs
•
Non-blocking switch matrix
– Patented ActiveArray™ matrix for superior performance
– Double-buffered configuration RAM cells for simultaneous
global updates
– ImpliedDisconnect™ function for single cycle disconnect/
connect
•
•
•
•
•
Full Broadcast and multicast capability
– One-to-One and One-to-Many connections
– Special broadcast mode routes one input to
all outputs at maximum data rate
•
Registered and flow-through data modes
– 333 MHz synchronous mode
– 667 Mb/s asynchronous mode
– Low jitter and signal skew
– Low duty cycle distortion
•
RapidConfigure™ parallel interface for
configuration and readback
•
JTAG serial interface for configuration and
Boundary Scan testing
•
792 TBGA package with 1.00mm ball spacing
•
Integrated Termination Resistors
Description
The OCX256 SRAM-based devices are non-blocking
128 X 128
digital crosspoint switches and are available in
LVDS (Low Voltage Differential Signaling) and LVPECL (Low Voltage PECL) versions. Both devices are
capable of data rates of 667 Megabits per second per port. The I/O ports are fixed as either input or output ports.
The input ports support flow-through mode only. The output ports are individually programmable to operate in
either flow-through (asynchronous) or registered (synchronous) mode. Each output register may be clocked by a
global clock or a next neighbor clock source.
The patented ActiveArray provides greater density, superior performance, and greater flexibility compared to a
traditional
n:1
multiplexer architecture. The OCX™ devices support various operating modes covering one input
to one output at a time as well as one input to many outputs, plus a special broadcast mode to program one input
to all outputs while maintaining maximum data rates. In all modes data integrity and connections are maintained
on all unchanged data paths.
The RapidConfigure parallel interface allows fast configuration of both the Output Buffers and the switch
matrix. Readback is supported for device test and verification purposes. The OCX256 also supports the industry
standard JTAG (IEEE 1149.1) interface for boundary scan testing. The JTAG interface can also be used to
download configuration data to the device and readback data. A functional block diagram of the OCX256 is
shown in Figure 1.
Applications
•
SONET/SDH and DWDM
•
Digital Cross-Connects
256
IN[127:0]
Input
Buffers
128 x 128
Crosspoint
Switch Matrix
•
System Backplanes and Interconnects
•
High Speed Test Equipment
256
OUT[127:0]
Output
Buffers
•
ATM Switch Cores
•
Video Switching
2 CLK
OE#
RapidConfigure
Signals
RCA[6:0] 7
RCB[6:0] 7
RCI[3:0] 4
RCO[4:0] 5
RC_CLK#
RC_EN#
UPDATE#
Configuration and
Programming Logic
TCK
TMS
TDI
TRST#
TDO
HW_RST#
JTAG
Signals
Figure 1 OCX256 Functional Block Diagram
Fairchild Semiconductor
[Rev. 2.0] 3/21/02
1
OCX256 Crosspoint Switch—Advanced Datasheet
(This page intentionally left blank)
2
[Rev. 2.0] 3/21/02
Fairchild Semiconductor
OCX256 Crosspoint Switch—Advanced Datasheet
Contents
1.
1.1
Introduction ........................................................................................................................... 7
Input and Output Buffers...................................................................................................... 8
Input and Output Port Function Mode ........................................................................... 8
Broadcast Mode ............................................................................................................. 9
1.1.1
1.1.2
1.2
Output Buffer Configuration ................................................................................................ 9
Output Control Signals................................................................................................... 9
Neighboring Output Port as a Clock Source .................................................................. 9
1.2.1
1.2.2
1.3
RapidConfigure Interface ....................................................................................................11
RapidConfigure Programming Instructions.................................................................. 11
1.3.1
1.4
JTAG Configuration Controller.......................................................................................... 14
JTAG Interface............................................................................................................. 14
Output Port Configuration ........................................................................................... 14
Switch Matrix Configuration ....................................................................................... 14
Mode Control Register Configuration.......................................................................... 14
JTAG Architecture and Shift Registers ........................................................................ 15
JTAG State Machine .................................................................................................... 16
JTAG Input Format ...................................................................................................... 16
JTAG Instructions ........................................................................................................ 17
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.5
1.6
2.
3.
3.1
3.2
4.
4.1
4.2
4.3
4.4
ImpliedDisconnect ............................................................................................................. 19
Device Reset Options ......................................................................................................... 20
Pin Description .....................................................................................................................21
Differential I/O Standards ...................................................................................................22
LVDS ................................................................................................................................. 22
LVPECL ............................................................................................................................. 23
Electrical Specifications .......................................................................................................24
Absolute Maximum Ratings .............................................................................................. 24
Recommended Operating Conditions ................................................................................ 24
Pin Capacitance ................................................................................................................. 24
DC Electrical Specifications .............................................................................................. 25
Fairchild Semiconductor
[Rev. 2.0] 3/21/02
3
OCX256 Crosspoint Switch—Advanced Datasheet
4.5
4.6
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
7.
8.
9.
AC Electrical Specifications............................................................................................... 26
Timing Diagrams................................................................................................................ 27
Package and Pinout ............................................................................................................. 31
Package Pinout ................................................................................................................... 31
Pinout by Ball Sequence..................................................................................................... 32
Pinout by Ball Name .......................................................................................................... 36
Package Dimensions........................................................................................................... 40
Package Thermal Characteristics........................................................................................ 42
Power Consumption ............................................................................................................ 43
Power for OCX256L (LVDS) ............................................................................................ 43
Power for OCX256P (LVPECL) ........................................................................................ 44
Component Availability and Ordering Information ......................................................... 45
Glossary ................................................................................................................................ 45
Product Status Definition .................................................................................................... 47
4
[Rev. 2.0] 3/21/02
Fairchild Semiconductor
OCX256 Crosspoint Switch—Advanced Datasheet
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
OCX256 Functional Block Diagram .................................................................................................... 1
OCX256 Switch Matrix ........................................................................................................................ 7
Input and Output Buffer Configuration ................................................................................................ 8
Next Neighbor Clock Block Diagram ................................................................................................ 10
OCX256 JTAG Architecture .............................................................................................................. 15
OCX256 JTAG State Machine ........................................................................................................... 16
OCX256L LVDS Signal Circuit......................................................................................................... 22
OCX256P LVPECL Signal Circuit .................................................................................................... 23
Registered Output Mode Timing ........................................................................................................ 27
Flow-Through Mode Timing .............................................................................................................. 27
Output Enable Timing ........................................................................................................................ 27
Duty Cycle Distortion ......................................................................................................................... 28
RapidConfigure Write Cycle .............................................................................................................. 28
RapidConfigure Read Cycle ............................................................................................................... 29
JTAG Timing ...................................................................................................................................... 29
Typical Performance at 667 Mb/s with PRBS Data ........................................................................... 30
OCX256 Package Pinout .................................................................................................................... 31
OCX256 Package—Bottom View ...................................................................................................... 40
OCX256 Package—Top and Side Views ........................................................................................... 41
Power Consumption Diagram for the OCX256L using LVDS .......................................................... 43
Power Consumption Diagram for the OCX256P using LVPECL...................................................... 44
Fairchild Semiconductor
[Rev. 2.0] 3/21/02
5
MEMS传感器
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
