Features
•
CPU32+ Processor (4.5 MIPS at 25 MHz)
– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)
– Background Debug Mode
– Byte-misaligned Addressing
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0 - 25 MHz Operation)
Slave Mode to Disable CPU32+ (Allows Use with External Processors)
– Multiple QUICCs Can Share One System Bus (One Master)
– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and
Intelligent Peripheral (22 MIPS at 25 MHz)
– Peripheral Device of TSPC603e (see DC415/D note)
Four General-purpose Timers
– Superset of MC68302 Timers
– Four 16-bit Timers or Two 32-bit Timers
– Gate Mode Can Enable/Disable Counting
Two Independent DMAs (IDMAs)
System Integration Module (SIM60)
Communications Processor Module (CPM)
Four Baud Rate Generators
Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)
Two SMC
V
CC
= +5V ± 5%
f
max
= 25 MHz and 33 MHz
Military Temperature Range: -55°C < T
C
< +125°C
P
D
= 1.4W at 25 MHz; 5.25V
2W at 33 MHz; 5.25V
•
•
•
•
•
32-bit Quad
Integrated
Communication
Controller
TS68EN360
•
•
•
•
•
•
•
•
•
•
Description
The TS68EN360 QUad Integrated Communication Controller (QUICC
™
) is a versatile
one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications activities.
The QUICC (pronounced “quick”) can be described as a next-generation TS68302
with higher performance in all areas of device operation, increased flexibility, major
extensions in capability, and higher integration. The term “quad” comes from the fact
that there are four serial communications controllers (SCCs) on the device; however,
there are actually seven serial channels: four SCCs, two serial management control-
lers (SMCs), and one serial peripheral interface (SPI).
Screening/Quality
This product is manufactured in full compliance with:
•
QML (class Q)
•
or according to Atmel standards
2113B–HIREL–06/05
R suffix
PGA 241
Ceramic Pin Grid Array Cavity Up
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier Cavity Down
1. Introduction
1.1
QUICC Architecture Overview
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family.
Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB).
The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common inter-
face for all modules of the TS68300 family, which allows the development of new devices more
quickly by using the library of existing modules. Although the IMB definition always included an
option for an on-chip 32-bit bus, the QUICC is the first device to implement this option.
The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each
module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in
Figure 1-1.
Figure 1-1.
QUICC Block Diagram
SIM 60
SYSTEM
PROTECTION
CPU32+
CORE
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
JTAG
BREAKPOINT
LOGIC
DRAM
CONTROLLER
AND
CHIP SELECTS
IMB (32 BIT)
EXTERNAL
BUS
INTERFACE
SYSTEM
I/F
CPM
COMMUNICATIONS PROCESSOR
RISC
CONTROLLER
TWO
IDMAs
FOURTEEN SERIAL
DMAs
SEVEN
SERIAL
CHANNELS
2.5-KBYTE
DUAL-PORT
RAM
INTERRUPT
CONTROLLER
FOUR
GENERAL-
PURPOSE
TIMERS
TIMER SLOT
ASSIGNER
OTHER
FEATURES
2
TS68EN360
2113B–HIREL–06/05
TS68EN360
3. Signal Description
3.1
Functional Signal Group
QUICC Functional Signal Groups
ADDRESS BUS
A27±A0
A31±A28/WE0±WE3
FC2±FC0/TM2±TM0
FC3/TT0
PORT A
RXD1/PA0
TXD1/PA1
RXD2/PA2
TXD2/PA3
L1TXDB/RXD3/PA4
L1RXDB/TXD3/PA5
L1TXDA/RXD4/PA6
L1RXDA/TXD4/PA7
TIMERs/SCCs/SIs/CLOCKs/BRG
TIN1/L1RCLKA/BRGO1/CLK1/PA8
BRGCLK1/TOUT1/CLK2/PA9
TIN2/L1TCLKA/BRGO2/CLK3/PA10
TOUT2/CLK4/PA11
TIN3/BRGO3/CLK5/PA12
BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13
TIN4/BRGO4/CLK7/PA14
L1TCLKB/TOUT4/CLK8/PA15
PORT B (PIP)
RRJCT1/SPISEL/PB0
RSTRT2/SPICLK/PB1
RRJCT2/SPIMOSI(SPITXD)/PB2
BRGO4/SPIMISO(SPIRXD)/PB3
DREQ1/BRGO1/PB4
DACK1/BRGO2/PB5
DONE1/SMTXD1/PB6
DONE2/SMRXD1/PB7
DREQ2/SMSYN1/PB8
DACK2/SMSYN2/PB9
L1CLKOB/SMTXD2/PB10
L1CLKOA/SMRXD2/PB11
L1ST1/RTS1/PB12
L1ST2/RTS2/PB13
L1ST3/L1RQB/RTS3/PB14
L1ST4/L1RQA/RTS4/PB15
STRBO/BRGO3/PB16
STRBI/RSTRT1/PB17
PORT C (INTERRUPT PARALLEL I/O)
L1ST1/RTS1/PC0
L1ST2/RTS2/PC1
L1ST3/L1RQB/RTS3/PC2
L1ST4/L1RQA/RTS4/PC3
CTS1/PC4
TGATE1/CD1/PC5
CTS2/PC6
TGATE2/CD2/PC7
SDACK2/L1TSYNCB/CTS3/PC8
L1RSYNCB/CD3/PC9
SDACK1/L1TSYNCA/CTS4/PC10
L1RSYNCA/CD4/PC11
DATA BUS
D31±D16
D15±D0
PRTY1±PRTY2/IOUT1±IOUT2
PRTY2/IOUT0/RQOUT
PRTY3/16BM
BUS CONTROL
SIZ0
SIZ1
DSACK0/TBI
DSACK1/TA
R/W
AS
DS/TT1
OE/AMUX
BUS ARBITRATION
RMC/CONFIG0/LOCK
BR
BG
BGACK/BB
BCLRO/CONFIG1/RAS2DD
SYSTEM CONTROL
QUICC
TS68360
240 PINS
RESETH
RESETS
HALT
BERR/TEA
PERR
INTERRUPT CONTROL
IRQ1/OUT0/RQOUT
IRQ4/OUT1
IRQ6/OUT2
IRQ2,3,5,7
AVEC/IACK5/AVECO
MEMORY CONTROLLER
CS6±CS0/RAS6±RAS0
CS/RAS7/IACK7
CAS3±CAS0/IACK6,3,2,1
TEST
TRIS/TS
BKPT/BKPT0/DSCLK
FREEZE/CONFIG2/MBARE
IPIPE1/RAS1DD/BCLRI
IPIPE0/BADD2/DSO
IFETCH/BADD3/DSI
TCK
TMS
TDI
TDO
TRST
CLOCK
XTAL
EXTAL
XFC
MODCK1±MODCK0
CLKO2±CLKO1
Figure 3-1.
5
2113B–HIREL–06/05
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