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74VHC373 Octal D-Type Latch with 3-STATE Outputs
April 2007
74VHC373
Octal D-Type Latch with 3-STATE Outputs
Features
■
High Speed: t
PD
=
5.0ns (typ) @ V
CC
=
5V
■
High Noise Immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
■
Power Down Protection is provided on all inputs
■
Low Noise: V
OLP
=
0.6V (Typ.)
■
Low Power Dissipation: I
CC
=
4µA (Max) @ T
A
=
25°C
■
Pin and Function Compatible with 74HC373
tm
General Description
The VHC373 is an advanced high speed CMOS octal
D-type latch with 3-STATE output fabricated with silicon
gate CMOS technology. It achieves the high speed oper-
ation similar to equivalent Bipolar Schottky TTL while
maintaining the CMOS low power dissipation. This 8-bit
D-type latch is controlled by a latch enable input (LE)
and an output enable input (OE). The latches appear
transparent to data when latch enable (LE) is HIGH.
When LE is LOW, the data that meets the setup time is
LATCHED. When the OE input is HIGH, the eight
outputs are in a high impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Ordering Information
Order Number
74VHC373M
74VHC373SJ
74VHC373MTC
Package
Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Outputs
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
74VHC373 Octal D-Type Latch with 3-STATE Outputs
Logic Symbol
IEEE/IEC
Functional Description
The VHC373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW, the latches store the information that
was present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the
2-state mode. When OE is HIGH, the standard outputs
are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
Truth Table
Inputs
LE
X
H
H
L
Outputs
D
n
X
L
H
X
OE
H
L
L
L
O
n
Z
L
H
O
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of
Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
Figure 1.
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
2
74VHC373 Octal D-Type Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±75mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(1)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
Parameter
Rating
2.0V to +5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
Note:
1. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
3
74VHC373 Octal D-Type Latch with 3-STATE Outputs
DC Electrical Characteristics
T
A
=
25°C
Symbol
V
IH
V
IL
V
OH
–40°C to +85°C
Max.
Min.
1.50
0.7 x V
CC
0.50
0.3 x V
CC
0.50
0.3 x V
CC
1.9
2.9
4.4
2.48
3.80
V
V
Parameter
HIGH Level
Input Voltage
LOW Level Input
Voltage
HIGH Level
Output
Voltage
V
CC
(V)
2.0
3.0–5.5
2.0
3.0–5.5
2.0
3.0
4.5
3.0
4.5
Conditions
Min.
1.50
0.7 x V
CC
Typ.
Max.
Units
V
V
IN
=
V
IH
I
OH
=
–50µA
or V
IL
I
OH
=
–4mA
I
OH
=
–8mA
V
IN
=
V
IH
I
OL
=
50µA
or V
IL
1.9
2.9
4.4
2.58
3.94
2.0
3.0
4.5
V
OL
LOW Level
Output Voltage
2.0
3.0
4.5
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.36
0.36
±0.25
0.1
0.1
0.1
0.44
0.44
±2.5
V
I
OL
=
4mA
I
OL
=
8mA
V
IN
=
V
IH
or V
IL
;
V
OUT
=
V
CC
or GND
V
IN
=
5.5V or GND
V
IN
=
V
CC
or GND
I
OZ
3-STATE Output
Off-State
Current
Input Leakage
Current
Quiescent
Supply Current
5.5
µA
I
IN
I
CC
0–5.5
5.5
±0.1
4.0
±1.0
40.0
µA
µA
Noise Characteristics
T
A
=
25°C
Symbol
V
OLP(2)
V
OLV(2)
V
IHD(2)
V
ILD(2)
Parameter
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Conditions
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
Typ.
0.6
–0.6
Limits
0.9
–0.9
3.5
1.5
Units
V
V
V
V
Note:
2. Parameter guaranteed by design.
©1993 Fairchild Semiconductor Corporation
74VHC373 Rev. 1.3
www.fairchildsemi.com
4
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