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74ACQ543• 74ACTQ543 Quiet Series Octal Registered Transceiver with 3-STATE Outputs
January 1990
Revised August 2000
74ACQ543• 74ACTQ543
Quiet Series
Octal Registered Transceiver
with 3-STATE Outputs
General Description
The ACQ/ACTQ543 is a non-inverting octal transceiver
containing two sets of D-type registers for temporary stor-
age of data flowing in either direction. Separate Latch
Enable and Output Enable inputs are provided for each
register to permit independent input and output control in
either direction of data flow.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance FACT Quiet Series
fea-
tures GTO
output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
8-bit octal latched transceiver
s
Separate controls for data flow in each direction
s
Back-to-back registers for storage
s
Outputs source/sink 24 mA
s
300 mil slim PDIP/SOIC
Ordering Code:
Order Number
74ACQ543SC
74ACQ543SPC
74ACTQ543SC
74ACTQ543QSC
74ACTQ543SPC
Package Number
M24B
N24C
M24B
MQA24
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code.
Connection Diagram
Pin Descriptions
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
–B
7
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
FACT, Quiet Series, FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010154
www.fairchildsemi.com
74ACQ543• 74ACTQ543
Logic Symbols
Functional Description
The ACQ/ACTQ543 contains two sets of eight D-type
latches, with separate input and output controls for each
set. For data flow from A to B, for example, the A-to-B
Enable (CEAB) input must be LOW in order to enter data
from A
0
–A
7
or take data from B
0
–B
7
, as indicated in the
Data I/O Control Table. With CEAB LOW, a LOW signal on
the A-to-B Latch Enable (LEAB) input makes the A-to-B
latches transparent; a subsequent LOW-to-HIGH transition
of the LEAB signal puts the A latches in the storage mode
and their outputs no longer change with the A inputs. With
CEAB and OEAB both LOW, the 3-STATE B output buffers
are active and reflect the data present at the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA inputs
IEEE/IEC
Data I/O Control Table
Inputs
Latch Status
CEAB
H
X
L
X
L
LEAB
X
H
L
X
X
OEAB
X
X
X
H
L
Latched
Latched
Transparent
—
—
High Z
—
—
High Z
Driving
Output Buffers
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACQ543• 74ACTQ543
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-up Source or
Sink Current
Junction Temperature (T
J
)
PDIP
140
°
C
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
±
300 mA
Recommended Operating
Conditions
Supply Voltage V
CC
ACQ
ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆
V/
∆
t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@3.0V, 4.5V, 5.5V
Minimum Input Edge Rate
∆
V/
∆
t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125 mV/ns
DC Electrical Characteristics for ACQ
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OLD
I
OHD
I
CC
(Note 4)
I
OZT
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Maximum I/O
Leakage Current
5.5
±
0.6
±
6.0
µA
5.5
5.5
5.5
5.5
8.0
0.002
0.001
0.001
T
A
= +25°C
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±
0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
V
IN
=
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
IN
=
V
IL
or V
IH
0.44
0.44
0.44
±
1.0
75
−75
80.0
µA
mA
mA
µA
V
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA (Note 2)
V
I
=
V
CC
,
GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
V
I
OUT
=
50
µA
V
I
OH
=
−12
mA
I
OH
=
−24
mA
I
OH
=
−24
mA (Note 2)
V
I
OUT
= −50 µA
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
Units
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
3
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74ACQ543• 74ACTQ543
DC Electrical Characteristics for ACQ
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Parameter
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
Typ
1.1
−0.6
3.1
1.9
(Continued)
T
A
= −40°C
to
+85°C
Guaranteed Limits
1.5
−1.2
3.5
1.5
V
V
V
V
Figures 1, 2
(Note 5)(Note 6)
Figures 1, 2
(Note 5)(Note 6)
(Note 5)(Note 7)
(Note 5)(Note 7)
T
A
= +25°C
Units
Conditions
Note 2:
Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 5:
Plastic DIP package.
Note 6:
Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7:
Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
V
IH
V
IL
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
OH
4.5
5.5
Maximum LOW Level
Output Voltage
V
OL
4.5
5.5
I
IN
I
OZT
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
Maximum I/O
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 9)
Maximum Quiescent Supply Current
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level Dynamic
Input Voltage
Maximum LOW Level Dynamic
Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
8.0
1.5
−1.2
2.2
0.8
0.6
0.36
0.36
±
0.1
±0.6
0.44
0.44
±
1.0
6.0
1.5
75
−75
80.0
µA
µA
mA
mA
mA
µA
V
V
V
V
V
4.5
5.5
0.001
0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
V
V
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
I
OH
=
−24
mA
I
OH
=
−24
mA (Note 8)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
I
OL
= 24 mA
I
OL
= 24 mA (Note 8)
V
I
=
V
CC
, GND
V
(OE)
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figures 1, 2
(Note 10)(Note 11)
Figures 1, 2
(Note 10)(Note 11)
(Note 10)(Note 12)
(Note 10)(Note 12)
Note 8:
Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 9:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 10:
DIP package
Note 11:
Max number of outputs defined as (n). (n−1) Data Inputs are driven 0V to 3V, one output @ GND.
Note 12:
Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=1
MHz.
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