Preliminary
FM21L16
2Mbit FRAM Memory
Features
2Mbit Ferroelectric Nonvolatile RAM
•
Organized as 128Kx16
•
Configurable as 256Kx8 Using /UB, /LB
•
10
14
Read/Write Cycles
•
NoDelay™ Writes
•
Page Mode Operation to 40MHz
•
Advanced High-Reliability Ferroelectric Process
SRAM Compatible
•
Industry Std. 128Kx16 SRAM Pinout
•
60 ns Access Time, 110 ns Cycle Time
Advanced Features
•
Low V
DD
Monitor Protects Memory against
Inadvertent Writes
•
Software Programmable Block Write Protect
Superior to Battery-backed SRAM Modules
•
No Battery Concerns
•
Monolithic Reliability
•
True Surface Mount Solution, No Rework Steps
•
Superior for Moisture, Shock, and Vibration
Low Power Operation
•
2.7V – 3.6V Power Supply
•
Low Current Mode (5µA) using ZZ pin
•
18 mA Active Current
Industry Standard Configuration
•
Industrial Temperature -40° C to +85° C
•
44-pin “Green”/RoHS TSOP-II package
Description
The FM21L16 is a 128Kx16 nonvolatile memory that
reads and writes like a standard SRAM. A
ferroelectric random access memory or FRAM is
nonvolatile, which means that data is retained after
power is removed. It provides data retention for over
10 years while eliminating the reliability concerns,
functional disadvantages, and system design
complexities of battery-backed SRAM (BBSRAM).
Fast write timing and high write endurance make
FRAM superior to other types of memory.
In-system operation of the FM21L16 is very similar
to other RAM devices and can be used as a drop-in
replacement for standard SRAM. Read and write
cycles may be triggered by /CE or simply by
changing the address. The FRAM memory is
nonvolatile due to its unique ferroelectric memory
process. These features make the FM21L16 ideal for
nonvolatile memory applications requiring frequent
or rapid writes in the form of an SRAM.
The FM21L16 includes a low voltage monitor that
blocks access to the memory array when V
DD
drops
below a critical threshold. The memory is protected
against an inadvertent access and data corruption
under this condition. The device also features
software-controlled write protection. The memory
array is divided into 8 uniform blocks, each of which
can be individually write protected.
The device is available in a 400 mil 44-pin TSOP-II
surface mount package. Device specifications are
guaranteed over industrial temperature range –40°C
to +85°C.
Pin Configuration
Ordering Information
FM21L16-60-TG
60 ns access, 44-pin
“Green”/RoHS TSOP-II
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.0
Sept. 2007
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
http://www.ramtron.com
Page 1 of 14
FM21L16 - 128Kx16 FRAM
16K x 16 block
Address Latch & Write Protect
16K x 16 block
Block & Row Decoder
16K x 16 block
16K x 16 block
A(16:0)
A(16:2)
16K x 16 block
16K x 16 block
A(1:0)
16K x 16 block
16K x 16 block
Column Decoder
CE
WE
UB, LB
OE
ZZ
2
I/O Latch & Bus Driver
Control
Logic
DQ(15:0)
Figure 1. Block Diagram
Pin Description
Pin Name
Type
A(16:0)
Input
/CE
Input
/WE
Input
/OE
/ZZ
Input
Input
DQ(15:0)
/UB
/LB
VDD
VSS
Rev. 1.0
Sept. 2007
I/O
Input
Input
Supply
Supply
Pin Description
Address inputs: The 17 address lines select one of 131,072 words in the FRAM array.
The lowest two address lines A(1:0) may be used for page mode read and write
operations.
Chip Enable input: The device is selected and a new memory access begins when /CE is
low and /ZZ is high. The entire address is latched internally on the falling edge of /CE.
Subsequent changes to the A(1:0) address inputs allow page mode operation when /CE
is low.
Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the
FM21L16 to write the data on the DQ bus to the FRAM array. The falling edge of /WE
latches a new column address for page mode write cycles.
Output Enable: When /OE is low, the FM21L16 drives the data bus when valid read
data is available. Deasserting /OE high tri-states the DQ pins.
Sleep: When /ZZ is low, the device enters a low power sleep mode for the lowest supply
current condition. Since this input is logically AND’d with /CE, /ZZ must be high for
normal read/write operation. If unused, tie /ZZ to V
DD
.
Data: 16-bit bi-directional data bus for accessing the FRAM array.
Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z
if /UB is high.
Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z
if /LB is high.
Supply Voltage: 3.3V
Ground
Page 2 of 14
FM21L16 - 128Kx16 FRAM
Functional Truth Table
1,2
/CE
/WE
A(16:2)
X
X
X
H
X
X
H
V
↓
L
H
No Change
L
H
Change
L
V
↓
L
V
↓
L
No Change
↓
X
X
↑
Notes:
1)
2)
3)
4)
H=Logic High, L=Logic Low, V=Valid Data, X=Don’t Care.
/WE-controlled write cycle begins as a Read cycle and A(16:2) is latched then.
Addresses A(1:0) must remain stable for at least 10 ns during page mode operation.
For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.
A(1:0)
X
X
V
Change
V
V
V
V
X
/ZZ
L
H
H
H
H
H
H
H
H
Operation
Sleep Mode
Standby/Idle
Read
Page Mode Read
Random Read
/CE-Controlled Write
/WE-Controlled Write
2
Page Mode Write
3
Starts Precharge
Byte Select Truth Table
/OE
/LB
/UB
H
X
X
X
H
H
L
H
L
L
H
L
L
X
H
L
L
H
L
L
Operation
Read; Outputs Disabled
Read; DQ(7:0) Hi-Z
Read; DQ(15:8) Hi-Z
Read
Write; Mask DQ(7:0)
Write; Mask DQ(15:8)
Write
Simplified Sleep/Standby State Diagram
Rev. 1.0
Sept. 2007
Page 3 of 14
FM21L16 - 128Kx16 FRAM
Overview
The FM21L16 is a wordwide FRAM memory
logically organized as 131,072 x 16 and accessed
using an industry standard parallel interface. All data
written to the part is immediately nonvolatile with no
delay. The device offers page mode operation which
provides higher speed access to addresses within a
page (row). An access to a different page requires that
either /CE transitions low or the upper address
A(16:2) changes.
Write Operation
Writes occur in the FM21L16 in the same time
interval as reads. The FM21L16 supports both /CE-
and /WE-controlled write cycles. In both cases, the
address A(16:2) is latched on the falling edge of /CE.
In a /CE-controlled write, the /WE signal is asserted
prior to beginning the memory cycle. That is, /WE is
low when /CE falls. In this case, the device begins the
memory cycle as a write. The FM21L16 will not
drive the data bus regardless of the state of /OE as
long as /WE is low. Input data must be valid when
/CE is deasserted high. In a /WE-controlled write, the
memory cycle begins on the falling edge of /CE. The
/WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be
driven if /OE is low, however it will hi-Z once /WE is
asserted low. The /CE- and /WE-controlled write
timing cases are shown in the Electrical
Specifications section.
Write access to the array begins on the falling edge of
/WE after the memory cycle is initiated. The write
access terminates on the rising edge of /WE or /CE,
whichever comes first. A valid write operation
requires the user to meet the access time specification
prior to deasserting /WE or /CE. Data setup time
indicates the interval during which data cannot
change prior to the end of the write access (rising
edge of /WE or /CE).
Unlike other truly nonvolatile memory technologies,
there is no write delay with FRAM. Since the read
and write access times of the underlying memory are
the same, the user experiences no delay through the
bus. The entire memory operation occurs in a single
bus cycle. Data polling, a technique used with
EEPROMs to determine if a write is complete, is
unnecessary.
Page Mode Operation
The FRAM array is organized as 8 blocks each
having 4096 rows. Each row has 4 column address
locations. Address inputs A(1:0) define the column
address to be accessed. An access can start on any
column address, and other column locations may be
accessed without the need to toggle the /CE pin. For
fast access reads, once the first data byte is driven
onto the bus, the column address inputs A(1:0) may
be changed to a new value. A new data byte is then
driven to the DQ pins no later than t
AAP
, which is less
than half the initial read access time. For fast access
writes, the first write pulse defines the first write
access. While /CE is low, a subsequent write pulse
Memory Operation
Users access 131,072 memory locations, each with 16
data bits through a parallel interface. The FRAM
array is organized as 8 blocks each having 4096 rows.
Each row has 4 column locations, which allows fast
access in page mode operation. Once an initial
address has been latched by the falling edge of /CE,
subsequent column locations may be accessed
without the need to toggle /CE. When /CE is
deasserted high, a precharge operation begins. Writes
occur immediately at the end of the access with no
delay. The /WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile
memory array immediately, which is a feature unique
to FRAM called NoDelay
TM
writes.
Read Operation
A read operation begins on the falling edge of /CE.
The falling edge of /CE causes the address to be
latched and starts a memory read cycle if /WE is high.
Data becomes available on the bus after the access
time has been satisfied. Once the address has been
latched and the access completed, a new access to a
random location (different row) may begin while /CE
is still low. The minimum cycle time for random
addresses is t
RC
. Note that unlike SRAMs, the
FM21L16’s /CE-initiated access time is faster than
the address cycle time.
The FM21L16 will drive the data bus when /OE and
at least one of the byte enables (/UB, /LB) is asserted
low. The upper data byte is driven when /UB is low,
and the lower data byte is driven when /LB is low. If
/OE is asserted after the memory access time has been
satisfied, the data bus will be driven with valid data.
If /OE is asserted prior to completion of the memory
access, the data bus will not be driven until valid data
is available. This feature minimizes supply current in
the system by eliminating transients caused by invalid
data being driven onto the bus. When /OE is
deasserted high, the data bus will remain in a high-Z
state.
Rev. 1.0
Sept. 2007
Page 4 of 14
FM21L16 - 128Kx16 FRAM
along with a new column address provides a page
mode write access.
Precharge Operation
The precharge operation is an internal condition in
which the state of the memory is being prepared for a
new access. Precharge is user-initiated by driving the
/CE signal high. It must remain high for at least the
minimum precharge time t
PC
.
Sleep Mode
The device incorporates a sleep mode of operation
which allows the user to achieve the lowest power
supply current condition. It enters a low power sleep
mode by asserting the /ZZ pin low. Read and write
operations must complete prior to the /ZZ pin going
low. Once /ZZ is low, all pins are ignored except the
/ZZ pin. When /ZZ is deasserted high, there is some
time delay (t
ZZEX
) before the user can access the
device.
If Sleep Mode is not used, the /ZZ pin should be tied
to V
DD
.
The data byte contains the write-protect settings. This
value will not be written to the memory array, so the
address is a don’t-care. Rather it will be held pending
the next cycle, which must be a write of the data
complement to the protection settings. If the
complement is correct, the write protect settings will
be adjusted. If not, the process is aborted and the
address sequence starts over. The data value written
after the correct six addresses will not be entered into
memory.
The protection data byte consists of 8-bits, each
associated with the write protect state of a sector. The
data byte must be driven to the lower 8-bits of the
data bus, DQ(7:0). Setting a bit to 1 write protects the
corresponding sector; a 0 enables writes for that
sector. The following table shows the write-protect
sectors with the corresponding bit that controls the
write-protect setting.
Write Protect Sectors – 16K x16 blocks
Sector 7
1FFFFh – 1C000h
Sector 6
1BFFFh – 18000h
Sector 5
17FFFh – 14000h
Sector 4
13FFFh – 10000h
Sector 3
0FFFFh – 0C000h
Sector 2
0BFFFh – 08000h
Sector 1
07FFFh – 04000h
Sector 0
03FFFh – 00000h
The write-protect read address sequence follows:
1.
12555h *
2.
1DAAAh
3.
01333h
4.
0ECCCh
5.
000FFh
6.
1FF00h
7.
1DAAAh
8.
0ECCCh
9.
0FF00h
10. 00000h
* If /CE is low entering the sequence, then an
address of 00000h must precede 12555h.
The address sequence provides a very secure way of
modifying the protection. The write-protect sequence
has a 1 in 3 x 10
32
chance of randomly accessing
exactly the 1
st
six addresses. The odds are further
reduced by requiring three more write cycles, one that
requires an exact inversion of the data byte. A flow
chart of the entire write protect operation is shown in
Figure 2. The write-protect settings are nonvolatile.
The factory default: all blocks are unprotected.
Software Write Protection
The 128Kx16 address space is divided into 8 sectors
(blocks) of 16Kx16 each. Each sector can be
individually software write-protected and the settings
are nonvolatile. A unique address and command
sequence invokes the write protection mode.
To modify write protection, the system host must
issue six read commands, three write commands, and
a final read command. The specific sequence of read
addresses must be provided in order to access to the
write protect mode. Following the read address
sequence, the host must write a data byte that
specifies the desired protection state of each sector.
For confirmation, the system must then write the
complement of the protection byte immediately
following the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a
seventh read address, or failing to complement the
protection value will leave the write protection
unchanged.
The write protect state machine monitors all
addresses, taking no action until this particular
read/write sequence occurs. During the address
sequence, each read will occur as a valid operation
and data from the corresponding addresses will be
driven onto the data bus. Any address that occurs out
of sequence will cause the software protection state
machine to start over. After the address sequence is
completed, the next operation must be a write cycle.
Rev. 1.0
Sept. 2007
Page 5 of 14
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