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74ACT841 10-Bit Transparent Latch with 3-STATE Outputs
November 1988
Revised September 2000
74ACT841
10-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACT841 bus interface latch is designed to eliminate
the extra packages required to buffer existing latches and
provide extra data width for wider address/data paths or
buses carrying parity. The ACT841 is a 10-bit transparent
latch, a 10-bit version of the ACT373.
Features
s
ACT841 has TTL-compatible inputs
s
Outputs source/sink 24 mA
s
Non-inverting 3-STATE outputs
Ordering Code:
Order Number
74ACT841SC
74ACT841MTC
74ACT841SPC
Package Number
M24B
MTC24
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.)
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
9
O
0
–O
9
OE
LE
Description
Data Inputs
3-STATE Outputs
Output Enable
Latch Enable
FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation
DS010156
www.fairchildsemi.com
74ACT841
Functional Description
The ACT841 consists of ten D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Function Table
Inputs
OE
X
H
H
H
L
L
L
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
NC
=
No Change
Internal
D
X
L
H
X
L
H
X
Q
X
L
H
NC
L
H
NC
Output
Function
O
Z
Z
Z
Z
L
H
NC
High Z
High Z
High Z
Latched
Transparent
Transparent
Latched
LE
X
H
H
L
H
H
L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74ACT841
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −
0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −
0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
PDIP
140
°
C
−
0.5V to
+
7.0V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
−
20 mA
+
20 mA
−
0.5V to V
CC
+
0.5V
±
50 mA
±
50 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
V/
∆
t)
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
Maximum 3-STATE
Leakage Current
Maximum
I
CC
/Input
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
5.5
5.5
8.0
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.5
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±5.0
1.5
75
−75
80.0
µA
µA
µA
mA
mA
µA
V
V
V
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Units
Conditions
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
3
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74ACT841
AC Electrical Characteristics
V
CC
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Parameter
Propagation Delay
D
n
to O
n
Propagation Delay
D
n
to O
n
Propagation Delay
LE to O
n
Propagation Delay
LE to O
n
Output Enable Time
OE to O
n
Output Enable Time
OE to O
n
Output Disable Time
OE to O
n
Output Disable Time
OE to O
n
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Typ
5.5
5.5
5.5
5.5
5.5
5.5
6.0
6.0
Max
9.5
9.5
9.0
9.0
9.5
9.5
10.5
10.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Min
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
Max
10.0
10.0
10.0
10.0
10.5
10.5
11.0
11.0
ns
ns
ns
ns
ns
ns
ns
ns
Units
(V)
(Note 4)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
AC Operating Requirements
V
CC
Symbol
t
S
t
H
t
W
Parameter
Setup Time, HIGH or LOW
D
n
to LE
Hold Time, HIGH or LOW
D
n
to LE
LE Pulse Width, HIGH
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
T
A
= +25°C
C
L
=
50 pF
Typ
−0.5
0.5
2.0
0.5
2.0
3.5
T
A
= −40°C
to
+85°C
C
L
=
50 pF
Guaranteed Minimum
1.0
2.0
3.5
ns
ns
ns
Units
(V)
(Note 5)
5.0
5.0
5.0
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation Capacitance
Typ
4.5
44
Units
pF
pF
Conditions
V
CC
=
OPEN
V
CC
=
5.0V
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