电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

7052L35PFGM

产品描述Application Specific SRAM, 2KX8, 35ns, CMOS, PQFP120
产品类别存储   
文件大小112KB,共11页
制造商IDT (Integrated Device Technology)
标准  
下载文档 详细参数 全文预览

7052L35PFGM概述

Application Specific SRAM, 2KX8, 35ns, CMOS, PQFP120

7052L35PFGM规格参数

参数名称属性值
是否无铅不含铅
是否Rohs认证符合
厂商名称IDT (Integrated Device Technology)
包装说明QFP, QFP120,.63SQ,16
Reach Compliance Codecompliant
最长访问时间35 ns
I/O 类型COMMON
JESD-30 代码S-PQFP-G120
JESD-609代码e3
内存密度16384 bit
内存集成电路类型APPLICATION SPECIFIC SRAM
内存宽度8
湿度敏感等级3
端口数量4
端子数量120
字数2048 words
字数代码2000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织2KX8
输出特性3-STATE
封装主体材料PLASTIC/EPOXY
封装代码QFP
封装等效代码QFP120,.63SQ,16
封装形状SQUARE
封装形式FLATPACK
并行/串行PARALLEL
峰值回流温度(摄氏度)260
电源5 V
认证状态Not Qualified
最大待机电流0.0018 A
最小待机电流2 V
最大压摆率0.3 mA
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层MATTE TIN
端子形式GULL WING
端子节距0.4 mm
端子位置QUAD
处于峰值回流温度下的最长时间30
Base Number Matches1

文档预览

下载PDF文档
HIGH-SPEED
2K x 8 FourPort
TM
STATIC RAM
Features
IDT7052S/L
High-speed access
– Commercial: 20/25/35ns (max.)
– Industrial: 25ns (max.)
– Military: 25/35ns (max.)
Low-power operation
– IDT7052S
Active: 750mW (typ.)
Standby: 7.5mW (typ.)
– IDT7052L
Active: 750mW (typ.)
Standby: 1.5mW (typ.)
True FourPort memory cells which allow simultaneous
access of the same memory locations
Fully asynchronous operation from each of the four ports:
P1, P2, P3, P4
Versatile control for write-inhibit: separate
BUSY
input to
control write-inhibit for each of the four ports
Battery backup operation—2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 120 pin and 132 pin Thin Quad Flatpacks and
108 pin PGA
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Description
The IDT7052 is a high-speed 2K x 8 FourPort™ Static RAM designed
to be used in systems where multiple access into a common RAM is
required. This FourPort Static RAM offers increased system performance
in multiprocessor systems that have a need to communicate in real time and
also offers added benefit for high-speed systems in which multiple access
is required in the same cycle.
Functional Block Diagram
R/W
P1
CE
P1
OE
P1
I/O
0P1
-I/O
7P1
BUSY
P1
PORT 1
ADDRESS
DECODE
LOGIC
PORT 2
ADDRESS
DECODE
LOGIC
PORT 4
ADDRESS
DECODE
LOGIC
PORT 3
ADDRESS
DECODE
LOGIC
COLUMN
I/O
COLUMN
I/O
R/W
P4
CE
P4
OE
P4
I/O
0P4
-I/O
7P4
BUSY
P4
A
0P1
- A
10P1
A
0P4
- A
10P4
MEMORY
ARRAY
A
0P2
- A
10P2
BUSY
P2
I/O
0P2
-I/O
7P2
OE
P2
CE
P2
R/W
P2
A
0P3
- A
10P3
BUSY
P3
COLUMN
I/O
COLUMN
I/O
I/O
0P3
-I/O
7P3
OE
P3
CE
P3
R/W
P3
2674 drw 01
JULY 2006
1
©2006 Integrated Device Technology, Inc.
DSC 2674/12

技术资料推荐更多

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 2684  164  1336  1776  524  55  4  27  36  11 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved