74VHC125 Quad Buffer with 3-STATE Outputs
May 2007
74VHC125
Quad Buffer with 3-STATE Outputs
Features
■
High Speed: t
PD
=
3.8ns (Typ.) at V
CC
=
5V
■
Lower power dissipation: I
CC
=
4 µA (Max.) at
■
■
■
■
tm
General Description
The VHC125 contains four independent non-inverting
buffers with 3-STATE outputs. It is an advanced high-
speed CMOS device fabricated with silicon gate CMOS
technology and achieves the high-speed operation simi-
lar to equivalent Bipolar Schottky TTL while maintaining
the CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply
voltage. This device can be used to interface 5V to 3V
systems and two supply systems such as battery
backup. This circuit prevents device destruction due to
mismatched supply and input voltages.
T
A
=
25°C
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(Min.)
Power down protection is provided on all inputs
Low noise: V
OLP
=
0.8V (Max.)
Pin and function compatible with 74HC125
Ordering Information
Order Number
74VHC125M
74VHC125MX_NL
(1)
74VHC125SJ
74VHC125MTC
74VHC125MTCX_NL
(1)
Package
Number
M14A
M14A
M14D
MTC14
MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number. Pb-Free package per JEDED J-STD-020B.
Note:
1. Device available in Tape and Reel only.
©1993 Fairchild Semiconductor Corporation
74VHC125 Rev. 1.3
www.fairchildsemi.com
74VHC125 Quad Buffer with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
T
STG
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current
DC V
CC
/ GND Current
Storage Temperature
Parameter
Rating
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to V
CC
+ 0.5V
–20mA
±20mA
±25mA
±50mA
–65°C to +150°C
260°C
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
(2)
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
IN
V
OUT
T
OPR
t
r
, t
f
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Input Rise and Fall Time,
V
CC
=
3.3V ± 0.3V
V
CC
=
5.0V ± 0.5V
Parameter
Rating
2.0V to +5.5V
0V to +5.5V
0V to V
CC
–40°C to +85°C
0ns/V
∼
100ns/V
0ns/V
∼
20ns/V
Note:
2. Unused inputs must be held HIGH or LOW. They may not float.
©1993 Fairchild Semiconductor Corporation
74VHC125 Rev. 1.3
www.fairchildsemi.com
3
74VHC125 Quad Buffer with 3-STATE Outputs
AC Electrical Characteristics
T
A
=
25°C
Symbol
t
PLH
, t
PHL
T
A
=
–40°C
to +85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Parameter
Propagation Delay
Time
V
CC
(V)
3.3 ± 0.3
5.0 ± 0.5
Conditions
C
L
=
15pF
C
L
=
50pF
C
L
=
15pF
C
L
=
50pF
Min.
Typ. Max.
5.6
8.1
3.8
5.3
5.4
7.9
3.6
5.1
9.5
6.1
8.0
11.5
5.5
7.5
8.0
11.5
5.1
7.1
13.2
8.8
1.5
1.0
4
6
14
10
Max. Units
9.5
13.0
6.5
8.5
9.5
13.0
6.0
8.0
15.0
10.0
1.5
1.0
10
pF
pF
pF
ns
ns
ns
ns
ns
ns
t
PZL
, t
PZH
3-STATE Output
Enable Time
3.3 ± 0.3 R
L
=
1kΩ C
L
=
15pF
C
L
=
50pF
5.0 ± 0.5
C
L
=
15pF
C
L
=
50pF
t
PLZ
, t
PHZ
3-STATE Output
Disable Time
3.3 ± 0.3 R
L
=
1kΩ C
L
=
50pF
5.0 ± 0.5
3.3 ± 0.3
(4)
5.0 ± 0.5
C
L
=
50pF
C
L
=
50pF
C
L
=
50pF
V
CC
=
Open
V
CC
=
5.0V
(5)
t
OSLH
, t
OSHL
Output to Output
Skew
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
Notes:
4. Parameter guaranteed by design. t
OSLH
=
|t
PLHmax
– t
PLHmin
|; t
OSHL
=
|t
PHLmax
– t
PHLmin
|.
5. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained by the equation:
I
CC
(Opr.)
=
C
PD
• V
CC
• f
IN
+ I
CC
/ 4 (per bit).
©1993 Fairchild Semiconductor Corporation
74VHC125 Rev. 1.3
www.fairchildsemi.com
5
FPGA/CPLD
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