HSDL-7000
IR 3/16 Encode/Decode IC
Data Sheet
Description
The HSDL-7000 performs the modulation/
demodulation function used to both encode and
decode the electrical pulses from the IR transceiver.
These pulses are then sent to a standard UART which
has a BAUDOUT signal available externally. This
signal is 16 times the selected baud rate. In
applications where the 16XCLK is not available, an
external means of generating the 16XCLK must be
designed.
The HSDL-7000 is comprised of two state machines –
the serial IR encode and the serial IR decode blocks.
Each of these blocks derives their timing from the
16XCLK input signal from the UART. The Encode
block is driven by the negative edge triggered TXD
signal from the UART. This initiates the modula-
tion state machine resulting in the 3/16 modulated
IR_TXD signal which drives the IR transceiver module.
The IR Decode block is driven by the negative edge
triggered IR_RCV signal from the infrared transceiver
module. After this signal is demodulated and
stretched, it drives the RCV signal to the UART.
Features
• Compliant with IrDA physical layer specs
• Interfaces with IrDA compliant SIR (115Kbps)
transceiver
• 1 Micron CMOS gate array
• Used in conjunction with standard 16550 UART
Applications
Interfaces with SIR infrared transceivers to perform:
• Serial half-duplex data transfer between:
Notebook computers
Subnotebooks
Desktops PCs
PDAs
Printers
Other peripheral devices
• Telecom applications in:
Modems
Fax machines
Pagers
Phones
• Industrial applications in:
Data collection devices
• Medical applications in:
Patient and pharmaceutical data collection
Schematic
HSDL-7000
Pin Out
16XCLK
1
2
3
4
8
7
6
5
V
CC
IR_TXD
IR_RCV
NRST
TXD
IR ENCODE
IR_TXD
TXD
RCV
GND
7000
YYWW
RCV
IR DECODE
IR_RCV
NRST
Pin Description
16XCLK -
Positive edge
triggered input clock that is set to
16 times the data transmission
baud rate. The encode and
decode schemes require this
signal. The signal is usually tied
to a UART’s BAUDOUT signal.
TXD -
Negative edge triggered
input signal; usually tied to a
UART’s SOUT signal (serial data
to be transmitted).
RCV -
Output signal which is
usually tied to a UART’s SIN
signal (received serial data).
GND -
Chip ground.
NRST -
Active low signal used to
reset the decode state machine.
This signal can be tied to POR
(Power on reset) or V
CC
. This
signal can also be used to disable
any data reception.
IR_RCV -
A 3/16th pulse width
input signal from the infrared
transceiver. The signal is a
demodulated (pulse stretched) to
generate the RCV output signal.
IR_TXD -
This signal is the
modulated 3/16ths TXD signal
which is input to the infrared
transceiver.
V
CC
-
Power.
Package Dimensions
1.05
(0.041)
6.65 (0.26)
MAX.
8
5
0.10
(0.004)
0.15 + 0.10/-0.00
(0.006 + 0.004/-0.00)
0.6 ± 0.2
(0.024 ± 0.008)
DETAIL A, SCALE 20
1
4
1.42
(0.056)
MAX.
1.55
(0.06)
SEE DETAIL A
0.40 + 0.10/-0.00
(0.016 + 0.004/-0.000)
5.60 (0.22)
1.27
(0.05)
7.7 ± 0.3
(0.30 ± 0.012)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
2
Encoding Scheme
16 CLOCK CYCLES
16 X CLOCK
TXD
7 cs
IRTXD
3 cs
The encoder sends a pulse for
every space or “0” that is sent on
the TXD line. On a high to low
transition of the TXD line, the
generation of the pulse is delayed
for 7 clock cycles of the 16XCLK
before the pulse is set high for 3
clock cycles (or 3/16th of a bit
time) and then subsequently
pulled low.
Decoding Scheme
16 CLOCK CYCLES
16 X CLOCK
IR_RXD
3 cs
RXD
A high to low transition of the
IR_RXD line from the infrared
transceiver module signifies a 3/
16th pulse. This pulse is
stretched to accommodate 1 bit
time (16 clock cycles). Every
pulse that is received is translated
into a “0” or space on the RXD
line equal to 1 bit time.
Note: The stretched pulse must
be at least 3/4 of a bit time in
duration to be correctly
interpreted by a UART.
3
Absolute Maximum Ratings
Parameter
Storage Temperature
Operating Temperature
Output Current
Power Dissipation
Input/Output Voltage
Power Supply Voltage
Symbol
T
S
T
A
I
O
P
MAX
V
I
/V
O
V
CC
Min.
-65
-40
Max.
+150
+85
10
0.22
V
CC
+ 0.5
+6.5
Units
°C
°C
mA
W
V
V
Conditions
-0.5
-0.5
Switching Specifications
(V
CC
= 5 Volts
±
10%, T
A
= -40 to +85°C)
Parameter
Toggle Frequency
Propagation Delay Time
Symbol
f
tog
t
pd
Min.
Typ.
120
0.5
1.0
2.0
1.42
1.54
Max.
Units
Mhz
ns
ns
ns
ns
ns
Conditions
Internal Gate
Input Buffer
Output Buffer
Output Buffer (C
L
= 15 pF)
Output Buffer (C
L
= 15 pF)
Output Fall Time
Output Rise Time
t
f
t
r
Note: f
tog
represents the maximum internal D-Type Flip Flop toggle rate
Capacitance
(V
CC
= 0 Volts, T
A
= -40 to +85°C)
Parameter
Input Capacitance
Output Capacitance
Output Fall Time
Symbol
C
IN
C
OUT
Min.
Typ.
10
10
10
Max.
20
20
20
Units
pF
pF
pF
Conditions
f = 1 MHz - Unmeasured Pins
Returned to 0 Volts
4
Recommended Operating Conditions
(T
A
= -40 to +85°C)
Parameter
Supply Voltage
Input Voltage
Ambient Temperature
High Level Input Voltage
Low Level Input Voltage
Positive Trigger Voltage
Negative Trigger Voltage
Hysteresis Voltage
Power Dissipation
Input Rise Time
Input Fall Time
Max Clk Frequency (16XCLK)
Minimum Pulse Width (IR_TXD)*
Symbol
V
CC
V
I
T
A
V
IH
V
IL
V
P
V
N
V
H
P
DISS
t
ri
t
fa
f
16XCLK
t
mpx
Min.
2.7
0.0
-40
0.7 V
CC
0.0
1.61
0.55
0.50
Typ.
5.0
Max.
5.5
V
CC
+85
V
CC
0.3 V
CC
4.00
3.10
2.00
220
200
200
2
Units
V
V
°C
V
V
V
V
V
mW
ns
ns
MHz
ns
Conditions
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
f
16XCLK
= 2 MHz
f
16XCLK
= 2 MHz
f
16XCLK
= 2 MHz
f
16XCLK
= 2 MHz
4.9
250
*IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7000’s internal state machine.
Under normal circumstances, this clock input should not exceed 16 * 115.2 Kbp/s or 1.8432 MHz. This product can operate at higher
clock rates, but the above is the recommended rate.
The Minimum Pulse Width represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA
specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3 * (1/1.8432 MHz) or 1.63
µs.
The minimum
pulse width specified for the HSDL-7000 is 250 ns, which is within IrDA specification. Under normal circumstances, the pulse width
should not be less than 1.63
µs.
Application Circuits
HSDL-7000 Connection to UART
SIR Transceivers
HSDL-7000
UART 16550
TXD
IR_TXD
TXD
SOUT
RCV
SIN
RCV
IR_RCV
16XCLK
BAUDOUT
At the time of this publication, Light Emitting Diodes (LEDs) that are contained in this product are
regulated for eye safety in Europe by the Commission for European Electrotechnical Standardization
(CENELEC) EN60825-1. Please refer to Application Brief I-008 for more information.
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