HCTL-2001-A00, HCTL-2017-A00 / PLC,
HCTL-2021-A00 / PLC
Quadrature Decoder/Counter Interface ICs
Data Sheet
Description
The HCTL-2xx1(7)-A00/PLC is CMOS ICs that performs
the quadrature decoder, counter, and bus interface
function. The HCTL-2xx1(7)-A00/PLC is designed to
improve system performance in digital closed loop
motion control systems and digital data input systems.
It does this by shifting time intensive quadrature
decoder functions to a cost effective hardware solution.
The HCTL-2xx1(7)-A00/PLC consists of a quadrature
decoder logic, a binary up/down state counter, and an
8-bit bus interface. The use of Schmitt-triggered CMOS
inputs and input noise filters allows reliable operation
in noisy environments. The HCTL-2001-A00 contains
12-bit counter and HCTL-2017-A00/PLC or HCTL-2021-
A00/PLC contains 16-bit counter and provides TLL/
CMOS compatible tri-state output buffers. Operation
is specified for a temperature range from –40 to +85°C
at clock frequencies up to 14MHz.
The HCTL-2021-A00/PLC provides quadrature decoder
output signals and cascade signals for use with many
standard computer ICs.
Features
•
Interfaces Encoder to Microprocessor
•
14 MHz Clock Operation
•
High Noise Immunity:
•
Schmitt Trigger Inputs and Digital Noise Filter
•
16-Bit Binary Up/Down Counter
•
Latched Outputs
•
8-Bit Tristate Interface
•
8, 12 or 16-Bit Operating Modes
•
Quadrature Decoder Output Signals, Up/Down and
Count
•
Cascade Output Signals, Up/Down and Count
•
Substantially Reduced System Software
•
5V Operation (V
DD
– V
SS
)
•
TTL/CMOS Compatible I/O
•
Operating Temperature: -40°C to 85°C
•
16-Pin PDIP, 20-Pin PDIP, 20-Pin PLCC
Applications
•
Interface Quadrature Incremental Encoders to
Microprocessors
•
Interface Digital Potentiometers to Digital Data
Input Buses
Part Number
HCTL-2001-A00
HCTL-2017-A00
HCTL-2017-PLC
HCTL-2021-A00
HCTL-2021-PLC
Description
14 MHz clock operation. 12-bit counter.
14 MHz clock operation. 16-bit counter.
14 MHz clock operation. 16-bit counter.
14 MHz clock operation. 16-bit counter.
Quadrature decoder output signals. Cascade output signals.
14 MHz clock operation. 16-bit counter.
Quadrature decoder output signals. Cascade output signals.
Pinout
PINOUT A
PINOUT A
PINOUT C
PINOUT B
PINOUT D
Package
PACKAGE A
PACKAGE A
PACKAGE C
PACKAGE B
PACKAGE C
Devices
PINOUT A
1
2
3
4
5
6
7
8
D0
CLK
SEL
OE
RST
CH B
CH A
VSS
VDD
D1
D2
D3
D4
D5
D6
D7
16
15
14
4
OE
U/D
NC
RST
CH B
CH A
VSS
D3
CNTdec
CNTcas
D4
D5
D6
D7
17
16
15
14
13
12
11
PINOUT B
1
2
3
D0
CLK
SEL
VDD
D1
D2
20
19
18
13
12
11
10
5
6
7
8
9
9
10
PINOUT C
PINOUT D
Package Dimensions
(dimension in mm)
See Appendix A.
2
Operating Characteristics
Table 1. Absolute Maximum Ratings
(All voltages below are referenced to V
SS
)
Parameter
DC Supply Voltage
Input Voltage
Storage Temperature
Operating Temperature
[1]
Symbol
V
DD
V
IN
T
S
T
A
Limits
-0.3 to +6.0
-0.3 to (VDD +0.3)
-55 to +150
-40 to +85
Units
V
V
C
C
Table 2. Recommended Operating Conditions
Parameter
DC Supply Voltage
Ambient Temperature
[1]
Symbol
V
DD
T
A
Limits
4.5 to 5.5
-40 to +85
Units
V
C
Table 3. DC Characteristics V
DD
= 5V ± 5%; T
A
= -40 to 85°C
Symbol
VIL
VIH
VT+
VT-
VH
IIN
VOH
VOL
IOZ
IDD
CIN
[3]
COUT
[3]
[2]
[2]
[2]
[2]
Parameter
Low-Level Input Voltage
High-Level Input Voltage
Schmitt-Trigger Positive-Going Threshold
Schmitt-Trigger Negative-Going Threshold
Schmitt-Trigger Hysteresis
Input Current
High-Level Output Voltage
Low-Level Output Voltage
High-Z Output Leakage Current
Quiescent Supply Current
Input Capacitance
Output Capacitance
Condition
Min
3.5
Typ
Max
1.5
Unit
V
V
V
V
V
3.5
1.0
1.0
VIN=VSS or VDD
IOH = -3.75 mA
IOL = +3.75mA
VO=VSS or VDD
VIN=Vss or VDD
Any Input
Any Output
-10
-10
2.4
1.5
2.0
1
4.5
0.2
1
1
5
5
4.0
+10
µA
V
V
µA
µA
pF
pF
0.4
+10
100
Notes:
1. Free Air
2. In general, for any V
DD
between the allowable limits (+4.5V to +5.5V), V
IL
= 0.3V
DD
and V
IH
= 0.7V
DD
; typical values are V
OH
= V
DD
– 0.5V
and V
OL
= V
SS
+ 0.2V
3. Including package capacitance
3
Functional Pin Description
Table 4a. Functional Pin Descriptions (PDIP Package)
Symbol
Pin
HCTL-
2001-
A00
VDD
VSS
CLK
CHA
CHB
RST
16
8
2
76
HCTL-
2017-
A00
16
8
2
76
HCTL-
2021-
A00
20
10
2
98
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter and
the position latch. It also resets the inhibit logic. RST is asynchronous with
respect to any other input signals.
This CMOS active low input enables the tri-state output buffers. The OE/
and SEL inputs are sampled by the internal inhibit logic on the falling edge
of the clock to control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch
is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also
control the internal inhibit logic.
SEL
0
1
BYTE SELECTED
High
Low
Description
5
5
7
OE
4
4
4
SEL
3
3
3
CNT
DCDR
U/D
NA
NA
NA
NA
16
5
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition. CNT
This LSTTL-compatible output allows the user to determine whether the IC
is counting up or down and is intended to be used with the CNTDCDR and
CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be
present before the rising edge of the CNTDCDR and CNTCAS outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2021-
A00 internal counter overflows or underflows. The rising edge on this
waveform may be used to trigger an external counter.
These LSTTL-compatible tri-state outputs form an 8-bit output ports through
which the contents of the 16-bit position latch may be read in 2 sequential
bytes. The High byte is read first followed by the Low bytes.
CNTCAS NA
NA
15
D0
D1
D2
D3
D4
D5
D6
D7
NC
1
15
14
13
12
11
10
9
NA
1
15
14
13
12
11
10
9
NA
1
19
18
17
14
13
12
11
6
Not connected - this pin should be left floating.
4
Table 4b. Functional Pin Descriptions (PLCC Package)
Symbol
Pin
HCTL
HCTL
2017-PLC 2021-PLC
VDD
VSS
CLK
CHA
CHB
RST
20
10
2
9
8
7
20
10
2
9
8
7
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter and the
position latch. It also resets the inhibit logic. RST is asynchronous with respect
to any other input signals.
This CMOS active low input enables the tri-state output buffers. The OE/ and SEL
inputs are sampled by the internal inhibit logic on the falling edge of the clock to
control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position latch is
enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL also control
the internal inhibit logic.
SEL
0
1
BYTE SELECTED
High
Low
Description
OE
4
4
SEL
3
3
CNTDCDR NA
U/D
NA
16
5
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition.
This LSTTL-compatible output allows the user to determine whether the IC is
counting up or down and is intended to be used with the CNTDCDR and CNTCAS
outputs. The proper signal U (high level) or D/ (low level) will be present before
the rising edge of the CNTDCDR and CNTCAS outputs.
A pulse is presented on this LSTTL-compatible output when the HCTL-2021-PLC
internal counter overflows or underflows. The rising edge on this waveform may
be used to trigger an external counter.
These LSTTL-compatible tri-state outputs form an 8-bit output ports through which
the contents of the 16-bit position latch may be read in 2 sequential bytes. The
High byte is read first followed by the Low bytes.
CNTCAS
NA
15
D0
D1
D2
D3
D4
D5
D6
D7
1
19
18
17
14
13
12
11
1
19
18
17
14
13
12
11
5
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