White Electronic Designs
High Density FLASH Memory Card
16, 32, 48, 64, 80 MEGABYTE
FEATURES
Low cost, high density Linear Flash Card
Universal 3V to 5V operating range providing full
“plug and play” exchangeability between different
systems
Based on Intel 28F128J3A (MLC) and *28F640J3
(MLC) Components
Fast Read Performance
• 250ns Maximum Access Time
• (200ns optional)
PCMCIA compatible
• x8/ x16 Data Interface
32-Byte Write Buffer (per Memory Device)
• 6μs per Byte Effective Write Time
128-bit Protection Register (per Memory Device)
• 64-bit Unique Device Identifier
• 64-bit User Programmable OTP Cells
Cross-Compatible Command Support
• Common Flash Interface (CFI)
• Intel Basic Command Set
• Scaleable Command Set
Power-Down Mode
• Reset, Power Down Registers
100,000 Erase Cycles per Block
128K word symmetrical Block Architecture
PC Card Standard Type I Form Factor
PCMCIA Flash Memory Card
FLF1 Series
information to be stored in a single cell. This leads to
reduced die size and reduced cost per megabyte.
WEDC’s FLF1 series cards are built with Intel’s 128Mb
memory components, 28F128J3A, with a manufacturer/
device ID of 89/18H. The FLF1 series is available in
densities of 32, 64, 96, 128, 160, and 192MB. There are
also 16MB and 48MB cards available built with Intel’s
64Mb memory components 28F640J3 with 89/17H
manufacturer/device ID.
The cards up to the 64MB density operate in the regular
PCMCIA mode. The densities beyond the 64MB density
are implemented using a “paging scheme”, which is also
supported by the PCMCIA standard. By writing a page
address to the Configuration Option Register (address
4000H), an additional page of memory can be accessed.
The current FLF1 series supports densities up to 192MB:
total of 3 pages: page 0 := 64MB, page 1 := 64MB, and
page 2 := 64MB.
The FLF1 series card operates in a wide, universal
voltage range, from 3V to 5V, allowing full “plug and play”
functionality and upgrade solutions in all mobile, battery
powered applications.
Each memory component in the card also has a 128-
bit Protection Register, containing 64 bits of User
Programmable OTP (One Time Programmable) Cells.
These cells can be programmed with a numeric security
measure, such as an electronic signature.
To provide a 16 bit word wide access supported by
the PCMCIA standard, devices are paired on the card.
Therefore, the Flash array is structured in 128K word
(256kB) blocks. Write, read and block erase operations can
be performed as either a word or byte wide operation.
The FLF1 series cards conform to the PC Card 95 Standard
supported by PCMCIA and JEIDA, providing electrical and
physical compatibility. The PC Card form factor offers an
industry standard pinout and mechanical outline, allowing
density upgrades without system design changes.
WEDC’s standard cards are shipped with WEDC’s Flash
Logo. Cards are also available with blank housings
(no Logo). The blank housings are available in both, a
recessed (for label) or
fl
at housing. Please contact your
WEDC sales representative for further information on
Custom artwork.
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
GENERAL DESCRIPTION
WEDC’s Flash memory cards — FLF1 Series — offer
high density linear Flash memory for code and data
storage, high performance disk emulation, mobile PC and
embedded applications.
The WEDC’s FLF1 series is based on Intel’s Multi Level
Cell (MLC) Flash memory technology, providing high
density Flash components at a significantly lower cost
per megabyte. MLC technology allows for two bits of
March 2003
Rev. 5
White Electronic Designs
PCMCIA Flash Memory Card
FLF1 Series
BLOCK DIAGRAM
N x 28F128J3A
Device Pair (N/2 - 1)
CLn
CH0
Device (N-1)
Device (N-2)
(B26)
A1-A23
+
ADDRESS BUS
(A1-A25)
(A1-A25)
A24, A25, B26
B26, (B27..)
D5-D0=Page Number (PN)
SRes
D7
M Res
WRi
RDi
CHn
Qn
Device Pair 1
CH0
Device 3
Device 2
CL1
CH0
CLn
CL0
Q2
Q0
Ctrl
Ai
LvReq
D6
D5
- Page Number (PN) -
D4
D3
D2
D1
D0
ADDRESS
BUFFER
A1-A25
Configuration Option Register: A=4000h (Read/Write)
WE#
OE#
control
logic
CE2#
CE1#
REG#
SR Clr
Reg Clr
ADDRESS Register NAME
4008h
4006h
4004h
4002h
Config. and Status Reg.
4000h
Configuration Option Register
At/Reg enable
Device Pair 0
CL0
CH0
Device 1
Device 0
4000h
Management
Registers
DATA
BUS
Q8-Q15
DATA
BUS
Q0-Q7
0000h
attrib. mem
CIS
E²PROM 2kB
control
Q0-Q7
I/O buffer
DATA
BUS
D8
-
D15
DATA
BUS
D0
-
D7
A0
Reset
220k
reset circuit
C
R
Vcc
M Res
SR Clr
Reg Clr
D0 - D15
CD1
CD2
(3V-5V)
Vcc
GND
WAIT
R/BUSY
VS1
VS2
BVD1
BVD2
Vpp2
Vpp1
N.C.
N.C.
R/B1
R/B0
OPEN
OPEN
10k
Vcc
OPEN
R/B(N-1)
Vcc
Configuration Option Register: ADRS=4000h
Read/Write
SRes
D7
D7
LvReq
- Page Number (PN) -
D2
D1
D0
D6
D5
D4
D3
Soft Reset, active High
1=Reset State
0=End Reset State
LevelReq (not supported)
Configuration index
D5-D1
reserved
D0
Page Number Config. (PN)
D6
D5-D0
Power On default =0
Configuration Status Register: ADRS=4002h
Read/Write
reserved
PwrDwn
reserved
D7
D6
D5
D4
D3
D2
D1
D0
D2
Power Down; active High
1 = Place all memory devices in power down mode
0 = normal operation
Power On default=0
CE1#, CE2#, OE#, WE#, Reg#:
A0:
Reset:
R/Busy - Open Drain output
pull up
pull down
pull down
pull up
typ 100k
typ 100k
typ 220k
typ 100k
Manufacturer ID
Device ID
Device ID
Intel
28F128J3A
28F640J3A
89
H
18
H
18
H
FLF1 Flash Card
based on Strata Flash 28F128J3A and 28F640J3
March 2003
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PINOUT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
RDY/BSY#
V
CC
V
PP
1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
O
I/O
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Ready/Busy
Supply Voltage
Prog. Voltage
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
HIGH
N.C.
LOW
LOW (1)
LOW
LOW
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
PCMCIA Flash Memory Card
FLF1 Series
Signal name
GND
CD1#
DQ11
DQ12
DQ13
DQ14
DQ15
CE2#
VS1
RFU
RFU
A17
A18
A19
A20
A21
V
CC
V
PP
2
A22
A23
A24
A25
VS2
RST
Wait#
RFU
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Reserved
Reserved
Active
LOW
LOW
NC (2)
I
I
I
I
I
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Prog. Voltage
NC
I
I
I
I
O
I
O
I
O
O
I/O
I/O
O
O
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Card Reset
Extended Bus cycle
Reserved
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
LOW
(2)
(3)
NC
HIGH
LOW(3)
Notes:
1. RDY/BSY# signal is an “Open drain” type output, pull-up resistors are required on
the host side.
2. VS
1
is connected to GND.
3. Wait#, BVD
1
and BVD
2
are internally connected to V
CC
by resistors for
compatibility.
MECHANICAL
1.6mm
0.063”
0.05
85.6mm 0.20
3.370”
1.0mm 0.05
0.039’
3.0mm
MIN.
Substrate area
54.0mm
2.126”
0.10
Pin #35
1.0mm 0.05
0.039’
Pin #1
10.0mm MIN.
0.400”
Interconnect area
3.3mm
0.130”
0.05”
5.0mm MAX.
0.197”
March 2003
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
Symbol
A0 - A25
DQ0 - DQ15
CE1#, CE2#
OE#
WE#
RDY/BSY#
Type
INPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
Name and Function
PCMCIA Flash Memory Card
FLF1 Series
Card Signal Description
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not
used in word access mode. A25 is the most significant bit
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ15 is the MSB.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2# enables odd byte accesses. Multiplexing A0,
CE1# and CE2# allows 8-bit hosts to access all data on DQ0 - DQ7 (see truth table).
OUTPUT ENABLE:
Active low signal gating read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Indicates status of internally timed erase or program algorithms. A high output indicates that
the card is ready to accept accesses. A low output indicates that one or more devices in the memory card are busy
with internally timed erase or write activities.
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are internally connected to ground on the
card. The host shall monitor these signals to detect card insertion (pulled-up on host side).
WRITE PROTECT:
Write protect reflects the status of the Write Protect switch on the memory card. WP set to high =
write protected, providing internal hardware write lockout to the Flash array. If card dOE#s not include optional write
protect switch, this signal will be pulled low internally indicating write protect = “off”.
PROGRAMMING VOLTAGES:
Not connected for 5V only card.
CARD POWER SUPPLY:
5.0V for all internal circuitry
CARD GROUND
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
ATTRIBUTE MEMORY SELECT :
Active low signal, enables access to attribute memory space, occupied by the
Card Information Structure (CIS) and Card Registers.
RESET:
Active high signal for placing card in Power-on default state. Reset can be used as a Power-Down control for
the memory array.
WAIT:
This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT:
These signals are pulled high to maintain SRAM card compatibility.
VOLTAGE SENSE:
Notifies the host socket of the card’s V
CC
requirements. VS1 and VS2 are
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD:
pin may be driven or left
fl
oating
CD1#, CD2#
WP
OUTPUT
OUTPUT
V
PP
1, V
PP
2
V
CC
GND
REG#
RST
WAIT#
BVD1, BVD2
VS1, VS2
RFU
NC
N.C.
Functional Truth Table
READ function
Function Mode
CE
2
#
CE
1
#
A
0
OE#
WE#
REG#
Common Memory
D
15
-D
8
D
7
-D
0
REG#
Attribute Memory
D
15
-D
8
D
7
-D
0
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
WRITE function
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
Odd-Byte Only Access
H
H
H
L
L
H
H
H
L
L
H
L
L
L
H
H
L
L
L
H
X
L
H
X
X
X
L
H
X
X
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
X
L
L
L
L
X
H
H
H
H
X
H
H
H
H
High-Z
High-Z
High-Z
Odd-Byte
Odd-Byte
X
X
X
Odd-Byte
Odd-Byte
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
X
Even-Byte
Odd-Byte
Even-Byte
X
X
L
L
L
L
X
L
L
L
L
High-Z
High-Z
High-Z
Not Valid
Not Valid
X
X
X
X
X
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
X
Even-Byte
X
Even-Byte
X
March 2003
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
CARD INTERFACE
The FLF0 series
fl
ash card complies with PC Card
standard (PCMCIA, March 1997). While maintaining
PCMCIA compatibility, the FLF0 series card has
integrated special features to extend functionality.
Card has built in 2 control registers:
• Configuration Option Register (COR)
Address = 4000
h
• Configuration and Status Register (CSR)
Address = 4002
h
COR register:
provide a soft reset function (bit D7) and
additional page register (bit D0) to extend card capacity
beyond 64MB.
SReset
As defined by PCMCIA, setting the SReset bit to 1,
places the card in the reset state. During this state
all memory devices are place in power down mode,
minimizing power consumption. Returning this bit to 0
leaves the reset cycle and place the card in the same
condition as following a power up or hardware reset.
This bit must be cleared to 0, to access any device on
the card.
Complete soft reset cycle must consist of a 2 step write
sequence to the SReset bit:
1. Initialization: write 1 to SReset
• reset cycle begin
• memory devices enters Power-Down mode
aborting all operations and clearing all registers.
2. Write 0 to SReset
• Reset cycle ends
• memory devices and registers enters power on
default state
Card can be place in Power Down mode by activating
Reset signal (pin58) or by controlling the bit D2 in CSR
register.
LevlRequest
Not supported
Configuration Index
Configuration Index bits (D0 - D5) are defined to provide
address extension bits -page address, to extend card
capacity beyond 64MB.
PCMCIA Flash Memory Card
FLF1 Series
Only bit D0 is supported:
• D1D0 set to 00bin (0H) selects:
page 0
• D1D0 set to 01bin (1H) selects:
page 1
• D1D0 set to 10bin (2H) selects:
page 2
• D1D0 set to 11bin (3H) selects:
page 3 (No
Memory Access)
D1D0 is set to the value of 00bin (0H) during any
reset cycle (Power on Reset, Hardware Reset,
and SReset). Attempting to access page 3 will not
result in the writing or reading of data.
CSR register:
provide a power control of memory array.
Only bit D2 is supported; all other bits are “don’t care”
PwrDwn
Writing 1 to PwrDwn bit (D2) forces each memory
device on the card into a reset/power down mode
by asserting all the devices RP# pins. Writing 0 to
the bit returns the array to stand by mode.
Card Information Structure (CIS) contains information
about Registers addressing and Memory structure.
Cards with memory capacity < 64MB do not support
Configuration Index bits.
Notes:
1. Reading from undefined address location or unsupported bits will return random
data.
2. Writing to undefined address location may result in card malfunctioning due to
limited address decoding.
3. See block diagram for more details about control registers.
Writing commands to the CUI enables reading of device data, query, identifier codes,
inspection and clearing of the status register, and, when V
PEN
= V
PENH
, block erasure,
program, and lock-bit configuration.
The Block Erase command requires appropriate command data and an address within
the block to be erased. The Byte/Word Program command requires the command
and address of the location to be written. Set Block Lock-Bit commands require the
command and block within the device to be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or the
fi
rst edge of CE
0
, CE
1
, or CE
2
that disables the
device. Standard microprocessor write timings are used.
For information regarding modes of operation,
commands, and programming details for the memory
components, please consult the Intel 28F128J3A
(28F640J3) data sheet.
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
March 2003
Rev. 5
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