LH28F004SU-NC
FEATURES
40-PIN TSOP
4M (512K × 8) Flash Memory
TOP VIEW
•
512K × 8 Word Configuration
•
5 V Write/Erase Operation (5 V V
PP
)
– No Requirement for DC/DC Converter
to Write/Erase
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE
RP
V
PP
RY/BY
A
18
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A
17
GND
NC
NC
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CC
V
CC
NC
DQ
3
DQ
2
DQ
1
DQ
0
OE
GND
CE
A
0
•
•
•
•
80 ns Maximum Access Time
32 Independently Lockable Blocks (16K)
100,000 Erase Cycles per Block
Automated Byte Write/Block Interface
– Command User Interface
– Status Register
»
– RY
/BY
»
Status Output
– Erase Suspend for Read
– Two-Byte Write
– Full Chip Erase
•
System Performance Enhancement
•
Data Protection
– Hardware Erase/Write Lockout during
Power Transitions
– Software Erase/Write Lockout
• Independently Lockable for Write/Erase
on Each Block (Lock Block and Protect
Set/Reset)
28F004SUT-NC80-1
Figure 1. TSOP Configuration
•
5 µA (Typ.) I
CC
in CMOS Standby
•
0.2 µA (Typ.) Deep Power-Down
•
State-of-the-Art 0.45 µm ETOX™ Flash
Technology
•
40-Pin, 1.2 mm × 10 mm × 20 mm
TSOP (Type I) Package
1
LH28F004SU-NC
4M (512K × 8) Flash Memory
DQ
0
- DQ
7
OUTPUT
BUFFER
INPUT
BUFFER
ID
REGISTER
DATA
QUEUE
REGISTER
I/O
LOGIC
OUTPUT
MULTIPLEXER
CSR
REGISTER
ESRs
CE
OE
CUI
WE
RP
DATA
COMPARATOR
A
0
- A
18
INPUT
BUFFER
Y-DECODER
Y GATING/SENSING
16KB BLOCK 30
16KB BLOCK 31
16KB BLOCK 0
16KB BLOCK 1
WSM
RY/BY
ADDRESS
QUEUE
LATCH
...
X-DECODER
...
ADDRESS
COUNTER
...
PROGRAM/
ERASE
VOLTAGE
SWITCH
V
PP
V
CC
GND
28F004SUT-NC80-2
Figure 2. LH28F004SU-NC Block Diagram
2
4M (512K × 8) Flash Memory
LH28F004SU-NC
PIN DESCRIPTION
SYMBOL
TYPE
NAME AND FUNCTION
WORD-SELECT ADDRESSES:
Select a word within one 16K block. These addresses
are latched during Data Writes.
BLOCK-SELECT ADDRESSES:
Select 1 of 32 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
DATA INPUT/OUTPUT:
Inputs data and commands during CUI write cycles. Outputs
array, buffer, identifier or status data in the appropriate Read mode. Floated when
the chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUTS:
Activate the device’s control logic, input buffers, decoders
and sense amplifiers. CE
»
must be low to select the device.
RESET/POWER-DOWN:
With RP
»
low, the device is reset, any current operation is
aborted and device is put into the deep power down mode. When the power is
turned on, RP
»
pin is turned to low in order to return the device to default config-
uration. When the power transition has occurred, or the power on/off, RP
» »
is
required to stay low in order to protect data from noise. When returning from Deep
Power-Down, a recovery time of 480 ns is required to allow these circuits to power-
up. When RP
»
goes low, any current or pending WSM operation(s) are terminated,
and the device is reset. All Status Registers return to ready (with all status flags
cleared). After returning, the device is in read array mode.
OUTPUT ENABLE:
Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
»
is high.
WRITE ENABLE:
Controls access to the CUI, Data Queue Registers and Address
Queue Latches. WE is active low, and latches both address and data (command
or array) on its rising edge.
READY/BUSY:
Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. When the WSM is ready for new operation or
Erase is Suspended, or the device is in deep power-down mode RY
»
/BY
»
pin is floated.
ERASE/WRITE POWER SUPPLY (5.0 V ±0.5 V):
For erasing memory array blocks or
writing words/bytes into the flash array.
DEVICE POWER SUPPLY (5.0 V ±0.5 V):
Do not leave any power pins floating.
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NO CONNECT:
No internal connection to die, lead may be driven or left floating.
A
0
- A
13
A
14
- A
18
INPUT
INPUT
DQ
0
- DQ
7
INPUT/OUTPUT
CE
»
INPUT
RP
»
INPUT
OE
»
INPUT
WE
INPUT
RY
»
/BY
»
OPEN DRAIN
OUTPUT
SUPPLY
SUPPLY
SUPPLY
V
PP
V
CC
GND
NC
3
LH28F004SU-NC
4M (512K × 8) Flash Memory
INTRODUCTION
Sharp’s LH28F004SU-NC 4M Flash Memory is a
revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and
communication products. With innovative capabilities,
5 V single voltage operation and very high read/write
performance, the LH28F004SU-NC is also the ideal
choice for designing embedded mass storage flash
memory systems.
The LH28F004SU-NC’s independently lockable 32
symmetrical blocked architecture (16K each) extended
cycling, low power operation, very fast write and read
performance and selective block locking provide a highly
flexible memory component suitable for cellular phone,
facsilime, game, PC, printer and handy terminal. The
LH28F004SU-NC’s single power supply operation en-
ables the design of memory cards which can be read/
written in 5.0 V systems. Its x8 architecture allows the
optimization of memory to processor interface. The flex-
ible block locking option enables bundling of executable
application software in a Resident Flash Array or
memory card. Manufactured on Sharp’s 0.45 µm
ETOX™ process technology, the LH28F004SU-NC is
the most cost-effective, high-density 5.0 V flash memory.
Internal Algorithm Automation allows Byte Writes and
Block Erase operations to be executed using a Two-
Write command sequence to the CUI in the same way
as the LH28F008SA 8M Flash memory.
A Superset of commands have been added to the
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
•
•
•
•
Software Locking of Memory Blocks
Memory Protection Set/Reset Capability
Two-Byte Serial Writes in 8-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed typically within
13 µs. A Block Erase operation erases one of the 32
blocks in typically 0.6 seconds, independent of the other
blocks.
LH28F004SU-NC allows to erase all unlocked blocks.
It is desirable in case of which you have to implement
Erase operation maximum 32 times.
LH28F004SU-NC enables Two-Byte serial Write
which is operated by three times command input. This
feature can improve system write performance by up to
typically 10 µs per byte.
All operations are started by a sequence of Write
commands to the device. Status Register (described in
detail later) and a RY
»
/BY
»
output pin provide informa-
tion on the progress of the requested operation.
Same as the LH28F008SA, LH28F004SU-NC re-
quires an operation to complete before the next opera-
tion can be requested, also it allows to suspend block
erase to read data from any other block, and allow to
resume erase operation.
The LH28F004SU-NC provides user-selectable block
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable OS or Ap-
plication Code. Each block has an associated non-vola-
tile lock-bit which determines the lock status of the block.
In addition, the LH28F004SU-NC has a software con-
trolled master Write Protect circuit which prevents any
modifications to memory blocks whose lock-bits are set.
When the device power-up or RP
»
turns High, Write
Protect Set/Confirm command must be written. Other-
wise, all lock bits in the device remain being locked,
can’t perform the Write to each block and single Block
Erase. Write Protect Set/Confirm command must be
written to reflect the actual lock status. However, when
the device power-on or RP
»
turns High, Erase All Un-
locked Blocks can be used. If used, Erase is performed
with reflecting actual lock status, and after that Write
and Block Erase can be used.
DESCRIPTION
The LH28F004SU-NC is a high performance 4M
(4,194,304 bit) block erasable non-volatile random
access memor y organized as 512K × 8. The
LH28F004SU-NC includes thirty-two 16K (16,384)
blocks. A chip memory map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F004SU-NC:
•
•
•
•
•
5 V Read, Write/Erase Operation (5 V V
CC
,V
PP
)
Low Power Capability
Improved Write Performance
Dedicated Block Write/Erase Protection
Command-Controlled Memory Protection
Set/Reset Capability
The LH28F004SU-NC will be available in a 40-pin,
1.2 mm thick × 10 mm × 20 mm TSOP (Type I) pack-
age. This form factor and pinout allow for very high board
layout densities.
A Command User Interface (CUI) serves as the sys-
tem interface between the microprocessor or
microcontroller and the internal memory operation.
4
4M (512K × 8) Flash Memory
LH28F004SU-NC
The LH28F004SU-NC contains Status Register to
accomplish various functions:
MEMORY MAP
•
A Compatible Status Register (CSR) which is 100%
compatible with the LH28F008SA Flash memory’s
Status Register. This register, when used alone, pro-
vides a straightforward upgrade capability to the
LH28F004SU-NC from a LH28F008SA based design.
The LH28F004SU-NC incorporates an open drain
RY
»
/BY
»
output pin. This feature allows the user to OR-
tie many RY
»
/BY
»
pins together in a multiple memory
configuration such as a Resident Flash Array.
The LH28F004SU-NC is specified for a maximum
access time of 80 ns (t
ACC
) at 5 V operation (4.5 to
5.5 V) over the commercial temperature range (0 to
+70°C).
The LH28F004SU-NC incorporates an Automatic
Power Saving (APS) feature which substantially reduces
the active current when the device is in static mode of
operation (addresses not switching).
In APS mode, the typical I
CC
current is 2 mA at 5.0 V.
A Deep Power-Down mode of operation is invoked
when the RP
»
(called PWD on the LH28F008SA) pin
transitions low, any current operation is aborted and the
device is put into the deep power down mode. This mode
brings the device power consumption to less than 5 µA,
and provides additional write protection by acting as a
device reset pin during power transitions. When the
power is turned on, RP
»
pin is turned to low in order to
return the device to default configuration. When the
power transition is occurred, or at the power on/off, RP
»
is required to stay low in order to protect data from noise.
A recovery time of 550 ns is required from RP
»
switch-
ing high until outputs are again valid. In the Deep Power-
Down state, the WSM is reset (any current operation
will abort) and the CSR register is cleared.
A CMOS Standby mode of operation is enabled when
CE
»
transitions high and RP
»
stays high with all input
control pins at CMOS levels. In this mode, the device
draws an I
CC
standby current of 10 µA.
7FFFFH
7C000H
7BFFFH
78000H
77FFFH
74000H
73FFFH
70000H
6FFFFH
6C000H
6BFFFH
68000H
67FFFH
64000H
63FFFH
60000H
5FFFFH
5C000H
5BFFFH
58000H
57FFFH
54000H
53FFFH
50000H
4FFFFH
4C000H
4BFFFH
48000H
47FFFH
44000H
43FFFH
40000H
3FFFFH
3C000H
3BFFFH
38000H
37FFFH
34000H
33FFFH
30000H
2FFFFH
2C000H
2BFFFH
2B000H
27FFFH
24000H
23FFFH
20000H
1FFFFH
1C000H
1BFFFH
18000H
17FFFH
14000H
13FFFH
10000H
0FFFFH
0C000H
0BFFFH
08000H
07FFFH
04000H
03FFFH
00000H
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
16KB BLOCK
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
28F004SUT-NC80-3
Figure 4. Memory Map
5
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