ICS548-05C
T1/E1 Clock Multiplier
Description
The ICS548-05C is a low-cost, low-jitter,
high-performace clock synthesizer designed to
produce x16 and x24 clocks from T1 and E1
frequencies. Using ICS’ patented analog/digital Phase-
Locked Loop (PLL) techniques, the device uses a
crystal or clock input to synthesize popular
communications frequencies. Power down modes allow
the chip to turn off completely, or the PLL and clock
output to be turned off separately.
ICS manuafactures the largest variety of
communications clock synthesizers for all applications.
Consult ICS to eliminate VCXO’s, crystals, and
oscillators from your board.
Features
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Packaged in 16-pin TSSOP
Ideal for telecom/datacom chips
Replaces oscillators
3.3 V or 5 V operation
Uses a crystal or clock input
Produces 24.704, 37.056, 32.768, or 49.152 MHz
Includes Power-down features
Advanced, low-power, sub-micron CMOS process
See also the MK2049-34 for generating
Industrial temperature range available
Block Diagram
MSEL
REFEN
PDCLK
X16 or x24
PLL/Clock
Synthesis
Circuitry
Input
Buffer/
Crystal
Oscillator
CLK
1.544 MHz or
X1/ICLK
2.048 MHz
clock or crystal
input
X2
REFOUT
Optional crystal
capacitors
MDS 548-05C B
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 072704
tel (408) 297-1201
●
www.icst.com
ICS548-05C
T1/E1 Clock Multiplier
Pin Assignment
X1/ICLK
VDD
VDD
REFEN
GND
GND
GND
VDD
1
2
3
4
5
6
7
8
16-pin TSSOP
16
15
14
13
12
11
10
9
X2
DC
REFOUT
MSEL
GND
PDCLK
DC
CLK
Output Clock Selection Table
MSEL
Pin 13
Input (MHz)
PIns 1, (16)
CLK (MHz)
PIn 9
0
1
0
1
1.544
1.544
2.048
2.048
24.704
37.056
32.768
49.152
Power Down Clock Selection Table
REFEN PDCLK
Pin 4
PIn 11
Power Down Selection Mode
0
0
1
1
0
1
0
1
The entire chip is off.
PLL and clock output run, REFOUT low.
REFOUT running, PLL off, CLK low.
All running.
Key: 0 = connect directly to GND; 1 = connect directly
to VDD
Pin Descriptions
Pin
Number
1
2, 3, 8
4
5, 6, 7, 12
9
10, 15
11
13
14
16
Pin
Name
X1/ICLK
VDD
REFEN
GND
CLK
DC
PDCLK
MSEL
REFOUT
X2
Pin
Type
XI
Power
Input
Power
—
Input
Input
XO
Pin Description
Crystal connection. Connect this pin to a crystal or clock input.
Connect to +3.3 V or +5 V. All VDD’s must be the same.
Reference Clock Enable. See table above. Connect to GND for best jitter/phase
noise.
Connect to ground.
Don’t Connect. Do not connect these pins to anything.
Power down clock. See table above.
Multiplier select pin. Selects x16 when low, x24 when high.
Crystal connection. Connect this pin to a crystal or leave unconnected for a clock.
Output Clock output set by input status of MSEL. See table above.
Output Buffered reference output clock. Controlled by REFEN.
Key: XI, XO = crystal connections; the in put pin MSEL must be tied directly to VDD or GND.
For a clock input, connect the input X1 and leave X2 unconnected (floating).
MDS 548-05C B
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 072704
tel (408) 297-1201
●
www.icst.com
ICS548-05C
T1/E1 Clock Multiplier
Application Information
Series Termination Resistor
Clock output traces should use series termination. To
series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
layout to see if the value of C should be changed. For a
clock input, leave X2 unconnected (floating).
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI and obtain the best signal integrity,
the 33Ω series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS548-05C.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
Decoupling Capacitors
As with any high performance mixed-signal IC, the
ICS548-05C must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF should be connected
between each VDD and GND on pins 3 and 5, as close
to the device as possible Other VDD’s can be
connected to pin 3. If reFOUT is not used, then REFEN
should be connected directly to ground.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(C
L
- 6) where C is the
load capacitor connected to X1 and X2, and C
L
is the
specified value of the load capacitance for the crystal.
A typical crystal C
L
is 18pF, so C = 2(18 - 6) = 24pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
MDS 548-05C B
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 072704
tel (408) 297-1201
●
www.icst.com
ICS548-05C
T1/E1 Clock Multiplier
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS548-05C. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70°C
-40 to +85°C
-65 to +150°C
125°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.15
Typ.
Max.
+70
5.5
Units
°C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature 0 to +70°C
Parameter
Core Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Supply Current
Power Down Supply
Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OH
V
OL
IDD
IDDPD
Conditions
X1/ICLK pin, clock
input only
X1/ICLK pin, clock
input only
Min.
3.15
(VDD/2)+1
Typ.
VDD/2
VDD/2
Max.
5.5
Units
V
V
(VDD/2)-1
V
V
2
0.8
I
OH
= -12 mA
CMOS level,
I
OH
= -4 mA
I
OL
= 12 mA
No Load
No Load
10
1
2.4
VDD-0.4
0.4
V
V
V
V
mA
µA
MDS 548-05C B
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 072704
tel (408) 297-1201
●
www.icst.com
ICS548-05C
T1/E1 Clock Multiplier
Parameter
Short Circuit Current
Input Capacitance
Frequency Synthesis Error
Symbol
I
OS
Conditions
CLK output
MSEL, PDCLK,
REFEN
Both selections
Min.
Typ.
±50
7
Max.
Units
mA
pF
0
ppm
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature 0 to +70°C
Parameter
Input Crystal or Clock
Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Start-up Time
Maximum Absolute Jitter,
short term
One Sigma Jitter
Symbol
Conditions
Min.
Typ.
1.544 or
2.048
Max.
Units
MHz
t
OR
t
OF
t
OD
20% to 80%
80% to 20%
At VDD/2
VDD = 3.3 V to CLK
stable
±100
25
40
50
1.5
1.5
60
10
ns
ns
%
ms
ps
ps
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
78
70
68
37
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 548-05C B
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 072704
tel (408) 297-1201
●
www.icst.com
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