r
r
TSL208R
512
y
1 LINEAR SENSOR ARRAY
TAOS031E
−
MAY 2007
D
D
D
D
D
D
D
D
D
512
×
1 Sensor-Element Organization
200 Dots-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 2000:1 (66 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 5 MHz
Single 5-V Supply
Replacement for TSL208
(TOP VIEW)
Description
The TSL208R linear sensor array consists of a 512
×
1
array of photodiodes and associated charge amplifier
circuitry. The pixels measure 120
μm
(H) by 70
μm
(W)
with 125-μm center-to-center spacing and 55-μm
spacing between pixels. Operation is simplified by
internal control logic that requires only a serial-input (SI)
signal and a clock.
1
2
3
4
5
6
7
V
DD
SI
CLK
AO
GND
SO
V
DD
The TSL208R is intended for use in a wide variety of applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear
and rotary encoding.
Functional Block Diagram
Pixel 1
S1
1 Integrator
Reset
2
2
Pixel
2
Pixel
3
Pixel
512
Output
Amplifier
4
R
L
330
W
AO
5
GND
1
V
DD
_
+
1
S2
Sample/
Output
3
Analog
Bus
Switch Control Logic
Gain
Trim
Q3
Q512
6
SO
Q1
Q2
CLK
SI
3
2
512-Bit Shift Register
The
LUMENOLOGY
r
Company
Texas Advanced Optoelectronic Solutions Inc.
1001 Klein Road
S
Suite 300
S
Plano, TX 75074
S
(972) 673-0759
r
www.taosinc.com
1
r
Copyright
E
2007, TAOS Inc.
TSL208R
512
y
1 LINEAR SENSOR ARRAY
TAOS031E
−
MAY 2007
Terminal Functions
TERMINAL
NAME
AO
CLK
GND
SI
SO
VDD
NO.
4
3
5
2
6
1, 7
I/O
O
I
I
I
O
I
Analog output.
Clock. The clock controls the charge transfer, pixel output and reset.
Ground (substrate). All voltages are referenced to the substrate.
Serial input. SI defines the start of the data out sequence.
Serial output. SO signals the end of the data out sequence.
Supply voltage for both analog and digital circuits.
DESCRIPTION
Detailed Description
The sensor consists of 512 photodiodes arranged in a linear array. Light energy impinging on a photodiode
generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During
the integration period, a sampling capacitor connects to the output of the integrator through an analog switch.
The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration
time. The integration time is the interval between two consecutive output periods.
The output and reset of the integrators is controlled by a 512-bit shift register and reset logic. An output cycle
is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)
†
. As the SI pulse
is clocked through the 512-bit shift register, the charge on the sampling capacitor of each pixel is sequentially
connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes
low, the pixel integrator is reset. On the 513
th
clock rising edge, the SI pulse is clocked out of the shift register
and the output assumes a high-impedance state. Note that this 513
th
clock pulse is required to terminate the
output of the 512
th
pixel and return the internal logic to a known state. A subsequent SI pulse can be presented
as early as the 514
th
clock pulse, thereby initiating another pixel output cycle.
The voltage developed at analog output (AO) is given by:
V
out
= V
drk
+ (R
e
) (E
e
) (t
int
)
where:
V
out
V
drk
R
e
E
e
t
int
is the analog output voltage for white condition
is the analog output voltage for dark condition
is the device responsivity for a given wavelength of light given in V/(μJ/cm
2
)
is the incident irradiance in
μW/cm
2
is integration time in seconds
AO is driven by a source follower with an internal 330-Ω pulldown resistor (no external resistor is required). The
output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When
the device is not in the output phase, AO is in a high impedance state.
A 0.1
μF
bypass capacitor should be connected between V
DD
and ground as close as possible to the device.
†
For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock.
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2007, TAOS Inc.
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TSL208R
512
y
1 LINEAR SENSOR ARRAY
TAOS031E
−
MAY 2007
Absolute Maximum Ratings
†
Supply voltage range, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to 6 V
Input voltage range, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to V
DD
+ 0.3V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−20
mA to 20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−25
mA to 25 mA
Voltage range applied to any output in the high impedance or
power-off state, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to V
DD
+ 0.3V
Continuous output current, I
O
(V
O
= 0 to V
DD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−25
mA to 25 mA
Continuous current through V
DD
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−100
mA to 100 mA
Analog output current range, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−25
mA to 25 mA
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−25°C
to 85°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−25°C
to 85°C
Lead temperature on connection pad for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
ESD tolerance, human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions (see Figure 1 and Figure 2)
MIN
Supply voltage, V
DD
Input voltage, V
I
High-level input voltage, V
IH
Low-level input voltage, V
IL
Wavelength of light source,
λ
Clock frequency, f
clock
Sensor integration time, t
int
Operating free-air temperature, T
A
Load capacitance, C
L
4.5
0
2
0
400
5
0.1026
0
NOM
5
MAX
5.5
V
DD
V
DD
0.8
1000
5000
100
70
330
UNIT
V
V
V
V
nm
kHz
ms
°C
pF
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2007, TAOS Inc.
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TSL208R
512
y
1 LINEAR SENSOR ARRAY
TAOS031E
−
MAY 2007
Electrical Characteristics at f
clock
= 1 MHz, V
DD
= 5 V, T
A
= 25°C,
λ
p
= 640 nm, t
int
= 5 ms,
R
L
= 330
Ω,
E
e
= 18
μW/cm
2
(unless otherwise noted)
PARAMETER
V
out
V
drk
PRNU
Analog output voltage (white, average over 512 pixels)
Analog output voltage (dark, average over 512 pixels)
Pixel response nonuniformity
Nonlinearity of analog output voltage
Output noise voltage
R
e
SE
V
sat
DSNU
IL
I
DD
I
IH
I
IL
V
O
OH
V
O
OL
C
i(SI)
C
i(CLK)
Responsivity
Saturation exposure
Analog output saturation voltage
Dark signal nonuniformity
Image lag
Supply current, output idle
High-level input current
Low-level input current
High-level
High level output voltage SO
voltage,
Low-level
Low level output voltage SO
voltage,
Input capacitance, SI
Input capacitance, CLK
V
I
= V
DD
V
I
= 0
I
O
= 50
μA
I
O
= 4 mA
I
O
= 50
μA
I
O
= 4 mA
4.5
4.95
4.6
0.01
0.4
40
40
0.1
All pixels
See Note 7
See Note 6
See Note 5
2.5
See Notes 2 & 3
See Note 3
See Note 4
16
TEST CONDITIONS
See Note 1
MIN
1.6
0
TYP
2
50
±
7%
±
0.4%
1
22
155
3.4
25
0.5%
28
45
10
10
mA
μA
μA
V
V
pF
pF
120
28
MAX
2.4
150
±
20%
FS
mVrms
V/
(μJ/cm
2
)
nJ/cm
2
V
mV
UNIT
V
mV
NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. Minimum saturation exposure is calculated using the minimum V
sat
, the maximum V
drk
, and the maximum R
e
.
6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
+
V out (IL)
*
V drk
V out (white)
*
V drk
100
Timing Requirements (see Figure 1 and Figure 2)
MIN
t
su(SI)
t
h(SI)
t
w
t
r
, t
f
Setup time, serial input (see Note 8)
Hold time, serial input (see Note 8 and Note 9)
Pulse duration, clock high or low
Input transition (rise and fall) time
20
0
50
0
500
NOM
MAX
UNIT
ns
ns
ns
ns
NOTES: 8. Input pulses have the following characteristics: t
r
= 6 ns, t
f
= 6 ns.
9. SI must go low before the rising edge of the next clock pulse.
Copyright
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2007, TAOS Inc.
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r
The
LUMENOLOGY
r
Company
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www.taosinc.com
TSL208R
512
y
1 LINEAR SENSOR ARRAY
TAOS031E
−
MAY 2007
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
t
s
t
pd(SO)
Analog output settling time to
±
1%
Propagation delay time, SO
TEST CONDITIONS
C
L
= 10 pF
MIN
TYP
185
50
MAX
UNIT
ns
ns
TYPICAL CHARACTERISTICS
CLK
SI
513 Clock Cycles
AO
Hi-Z
t
w
CLK
t
su(SI)
SI
AO
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hi-Z
Figure 1. Timing Waveforms (each section)
1
2
512
513
2.5 V
5V
0V
5V
0V
50%
t
h(SI)
t
s
t
s
Pixel 1
Pixel 512
Figure 2. Operational Waveforms (each section)
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2007, TAOS Inc.
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