82C284
March 1997
Clock Generator and Ready Interface
for 80C286 Processors
Description
The Intersil 82C284 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with
hysteresis.
Features
• Generates System Clock for 80C286 Processors
• Generates System Reset Output from Schmitt
Trigger Input
- Improved Hysteresis
• Uses Crystal or External Signal for Frequency Source
• Dynamically Switchable between Two Input
Frequencies
• Provides Local READY and MULTIBUS
®
READY
Synchronization
• Static CMOS Technology
• Single +5V Power Supply
• Available in 18 Lead CerDIP Package
Ordering Information
PART NUMBER
CD82C284-12
ID82C284-10
ID82C284-12
TEMP. RANGE
0
o
C to +70
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PACKAGE
PKG.
NO.
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
18 Ld CERDIP F18.3
Pinout
82C284 (CERDIP)
TOP VIEW
Functional Diagram
RESET
ARDY
SRDY
SRDYEN
READY
EFI
F/C
X1
X2
GND
1
2
3
4
5
6
7
8
9
18 VCC
17 ARDYEN
16 S1
15 S0
14 NC
13 PCLK
12 RESET
11 RES
10 CLK
EFI
F/C
ARDYEN
ARDY
X1
X2
XTAL
OSC
MUX
RES
SYNCHRONIZER
RESET
CLK
SYNCHRONIZER
SRDYEN
SRDY
READY LOGIC
READY
S1
S0
PCLK GENERATOR
PCLK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
©
Intersil Corporation 1999
MULTIBUS
File Number
2966.1
®
is a patented Intel bus.
1
82C284
Pin Description
The following pin function descriptions are for the 82C284 clock generator.
PIN
SYMBOL
CLK
NUMBER
10
TYPE
O
DESCRIPTION
SYSTEM CLOCK: the signal used by the processor and support devices which must be synchro-
nous with the processor. The frequency of the CLK output has twice the desired internal processor
clock frequency. CLK can drive both TTL and CMOS level inputs.
FREQUENCY/CRYSTAL SELECT: this pin selects the source for the CLK output. When there is a
LOW level on this input, the internal crystal oscillator drives CLK. When there is a HIGH level on F/C,
the EFI input drives the CLK input. This pin can be dynamically switched, which allows changing the
processor CLK frequency while running for low-power operation, etc.
CRYSTAL IN: the pin stop which parallel resonant, fundamental mode crystal is attached for the in-
ternal oscillator. When F/C is LOW, the internal oscillator will drive the CLK output at the crystal fre-
quency. The crystal frequency must be twice the desired internal processor clock frequency.
EXTERNAL FREQUENCY IN: drives CLK when the F/C input is HIGH. The EFI input frequency
must be twice the desired internal processor clock frequency.
PERIPHERAL CLOCK: the output which provides a 50% duty cycle clock with one-half the frequen-
cy of CLK. PCLK will be in phase with the internal processor clock following the first bus cycle after
the processor has been reset.
ASYNCHRONOUS READY ENABLE: an active LOW input which qualifies the ARDY input.
ARDYEN selects ARDY as the source of READY for the current bus cycle. Inputs to ARDYEN may
be applied asynchronously to CLK. Setup and hold times are given to assure a guaranteed response
to synchronous outputs.
ASYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The ARDY
input is qualified by ARDYEN. Inputs to ARDY may be applied asynchronously to CLK. Setup and
hold times are given to assure a guaranteed response to synchronous outputs.
SYNCHRONOUS READY ENABLE: an active LOW input which qualifies SRDY. SRDYEN selects
SRDY as the source for READY to the CPU for the current bus cycle. Setup and hold time must be
satisfied for proper operation.
SYNCHRONOUS READY: an active LOW input used to terminate the current bus cycle. The SRDY
input is qualified by the SRDYEN input. Setup and hold time must be satisfied for proper operation.
READY: an active LOW output which signals to the processor that the current bus cycle is to be com-
pleted. The SRDY SRDYEN, ARDY, ARDYEN, S1, S0, and RES inputs control READY as explained
later in the READY generator section. READY is an open drain output requiring an external pull-up
resistor.
STATUS: these inputs prepare the 82C284 for a subsequent bus cycle. S0 and S1 synchronize
PCLK to the internal processor clock and control READY. Setup and hold times must be satisfied for
proper operation
RESET: an active HIGH output which is derived from the RES input RESET is used to force the sys-
tem into an initial state. When RESET is active, READY will be active (LOW).
RESET IN: an active LOW input which generates the system reset signal (RESET). Signals to RES
may be applied asynchronously to CLK. A Schmitt trigger input is provided on RES, so that an RC
circuit can be used to provide a time delay. Setup and hold times are given to assure a guaranteed
response to synchronous inputs.
SYSTEM POWER: The +5V Power Supply Pin. A 0.1µF capacitor between V
CC
and GND is recom-
mended for decoupling.
SYSTEM GROUND: 0V
F/C
6
I
X1, X2
7, 8
I
EFI
5
I
PCLK
13
O
ARDYEN
17
I
ARDY
1
I
SRDYEN
3
I
SRDY
2
I
READY
4
O
S0, S1
15,16
I
RESET
12
O
RES
11
I
V
CC
GND
18
9
2
82C284
Functional Description
Introduction
The 82C284 generates the clock, ready, and reset signals
required for 80C286 processors and support components.
The 82C284 is packaged in an 18-pin DIP and contains a
crystal controlled oscillator, clock generator, peripheral clock
generator, MULTIBUS® ready synchronization logic, and
system reset generation logic.
Clock Generator
The CLK output provides the basic timing control for an
80C286 system. CLK has output characteristics sufficient to
drive CMOS devices. CLK is generated by either an internal
crystal oscillator, or an external source as selected by the
F/C input pin. When F/C is LOW, the crystal oscillator drives
the CLK output. When F/C is HIGH, the EFI input drives the
CLK output.
The F/C pin on the Intersil 82C284 is dynamically switch-
able. This allows the CLK frequency to the processor to be
changed from one frequency to another in a running system.
With this feature, a system can be designed which operates
at maximum speed when needed, and then dynamically
switched to a lower frequency to implement a low-power
mode. The lower frequency can be anything down to, but
excluding, DC. The following 3 conditions apply when
dynamically switching the F/C pin (see Figure 1):
1)
The CLK is stretched in the low portion of the
φ2
phase
of its cycle during transition from one CLK frequency to
the other (see Waveforms).
2)
When switching CLK frequency sources, there is a max-
imum transition latency of 2.5 clock cycles of the fre-
quency being switched to, from the time CLK freezes
low, until CLK restarts at the new frequency (see Wave-
forms).
The maximum latency from the time F/C is dynamically
switched, to the time CLK freezes low, is 4 CLK cycles
(see Waveforms).
3)
The following steps describe the sequence of events that
transpire when F/C is dynamically switched:
A)
F/C switched from high (using EFI input) to low (using
the crystal input X1 - see Figure 1A).
1) The state of F/C is sampled when both CLK and
PCLK are high until a change is detected.
2) On the second following falling edge of PCLK, CLK is
frozen low.
3) CLK restarts at the crystal frequency on the rising
edge of Xl, after the second falling edge of X1.
B)
F/C switched from low (using the crystal input Xl) to high
(using the EFI input - see Figure 1B).
1) The state of F/C is sampled when both CLK and
PCLK are high until a change is detected.
2) On the second following falling edge of PCLK, CLK is
frozen low.
3) CLK restarts at the EFI input frequency on the falling
edge of EFl after the second rising edge of EFI.
φ1
1
CLK
φ2
φ1
φ2
φ1
φ2
PCLK
2
F/C
X1
3
FIGURE 1A. F/C SWITCHED FROM HIGH (USING EFI INPUT) TO LOW (USING THE CRYSTAL INPUT X1)
3
82C284
1
CLK
φ1
φ2
φ1
2
φ2
φ1
φ2
PCLK
F/C
EFI
3
FIGURE 1B. F/C SWITCHED FROM LOW (USING THE CRYSTAL INPUT X1) TO HIGH (USING THE EFI INPUT)
FIGURE 1. DYNAMICALLY SWITCHING THE F/C PIN
The 82C284 provides a second clock output, PCLK, for periph-
eral devices. PCLK is CLK divided by two. PCLK has a duty
cycle of 50% and CMOS output drive characteristics. PCLK is
normally synchronized to the internal processor clock.
After reset, the PCLK signal may be out of phase with the inter-
nal processor clock. The S1 and S0 signals of the first bus
cycle are used to synchronize PCLK to the internal processor
clock. The phase of the PCLK output changes by extending its
HIGH time beyond one system clock (see waveforms). PCLK is
forced HIGH whenever either S0 or S1 were active (LOW) for
the two previous CLK cycles. PCLK continues to oscillate when
both S0 and S1 are HIGH.
Since the phase of the internal processor clock will not change
except during reset, the phase of PCLK will not change except
during the first bus cycle after reset.
Oscillator
The oscillator circuit of the 82C284 is a linear Pierce oscillator
which requires an external parallel resonant, fundamental
mode, crystal. The output of the oscillator is internally buffered.
The crystal frequency chosen should be twice the required
internal processor clock frequency. The crystal should have a
typical load capacitance of 32pF.
X1 and X2 are the oscillator crystal connections. For stable
operation of the oscillator, two loading capacitors are recom-
mended, as shown in Table 1. The sum of the board capaci-
tance and loading capacitance should equal the values shown.
It is advisable to limit stray board capacitances (not including
the effect of the loading capacitors or crystal capacitance) to
less than 10pF between the X1 and X2 pins. Decouple V
CC
and GND as close to the 82C284 as possible with a 0.1µF poly-
carbonate capacitor.
TABLE 1. 82C284 CRYSTAL LOADING CAPACITANCE VALUES
Cl
CAPACITANCE
(PIN 7)
60pF
25pF
15pF
C2
CAPACITANCE
(PIN 8)
40pF
15pF
15pF
CLK Termination
Due to the CLK output having a very fast rise and fall time, it is
recommended to properly terminate the CLK line at frequen-
cies above 10MHz to avoid signal reflections and ringing. Ter-
mination is accomplished by inserting a small resistor
(typically 10-74Ω) in series with the output, as shown in Figure
2. This is known as series termination. The resistor value plus
the circuit output impedance (approximately 25Ω) should be
made equal to the impedance of the transmission line.
CLK
OUT
R
Z
CLOSELY
PLACED
LOADS
RO
≈
25
TRANSMISSION
LINE
Z
CLOSELY
PLACED
LOADS
FIGURE 2. SERIES TERMINATION
Reset Operation
The reset logic provides the RESET output to force the sys-
tem into a known, initial state. When the RES input is active
(LOW), the RESET output becomes active (HIGH), RES is
synchronized internally at the falling edge of CLK before
generating the RESET output (see waveforms). Synchroni-
zation of the RES input introduces a one or two CLK delay
before affecting the RESET Output.
At power up, a system does not have a stable V
CC
and CLK.
To prevent spurious activity, RES should be asserted until
V
CC
and CLK stabilize at their operating values. 80C286
processors and support components also require their
RESET inputs be HIGH a minimum of 16 CLK cycles. An RC
network, as shown in Figure 3, will keep RES LOW long
enough to satisfy both needs.
A Schmitt trigger input with hysteresis on RES assures a single
transition of RESET with an RC circuit on RES. The hysteresis
separates the input voltage level at which the circuit output
switches from HIGH to LOW from the input voltage level at
which the circuit output switches from LOW to HIGH. The RES
HIGH to LOW input transition voltage is lower than the RES
CRYSTAL
FREQUENCY
1MHz to 8MHz
8MHz to 20MHz
20MHz to 25MHz
4
82C284
LOW to HIGH input transition voltage. As long as the slope of
the RES input voltage remains in the same direction (increas-
ing or decreasing) around the RES input transition voltage, the
RESET output will make a single transition.
V
CC
C1
82C284
11
47Ω
+
10µF
RES
6
F/C
7
X1
8
X2
82C284
4
READY
V
CC
1N914
10kΩ
18
READY
V
CC
DECOUPLING
CAPACITOR
CLK
V
CC
10
CLK
80C286
CPU OR
SUPPORT
COMPONENT
FIGURE 4. RECOMMENDED CRYSTAL AND READY
CONDITIONS
FIGURE 3. TYPICAL RC RES TIMING CIRCUIT
Ready Operation
The 82C284 accepts two ready sources for the system ready
signal which terminates the current bus cycle. Either a synchro-
nous (SRDY) or asynchronous ready (ARDY) source may be
used. Each ready input has an enable (SRDYEN and
ARDYEN) for selecting the type of ready source required to ter-
minate the current bus cycle. An address decoder would nor-
mally select one of the enable inputs.
READY is enabled (LOW), if either SRDY + SRDYEN = 0 or
ARDY + ARDYEN = 0 when sampled by the 82C284 READY
generation logic. READY will remain active for at least two CLK
cycles.
The READY output has an open-drain driver allowing other
ready circuits to be wired with it, as shown in Figure 4. The
READY signal of an 80C286 system requires an external
pull-up resistor. To force the READY signal inactive (HIGH)
at the start of a bus cycle, the READY output floats when
either S1 or S0 are sampled LOW at the falling edge of CLK.
Two system clock periods are allowed for the pull-up resistor
to pull the READY signal to V
lH
. When RESET is active,
READY is forced active one CLK later (see Waveforms).
Figure 5 illustrates the operation of SRDY and SRDYEN.
These inputs are sampled on the falling edge of CLK when
S1 and S0 are inactive and PCLK is HIGH. READY is forced
active when both SRDY and SRDYEN are sampled as LOW.
Figure 6 shows the operation of ARDY and ARDYEN These
inputs are sampled by an internal synchronizer at each fall-
ing edge of CLK. The output of the synchronizer is then sam-
pled when PCLK is HIGH. If the synchronizer resolved both
the ARDY and ARDYEN as active, the SRDY and SRDYEN
inputs are ignored. Either ARDY or ARDYEN must be HIGH
at the end of T
S
, therefore, at least one wait state is required
when using the ARDY and ARDYEN inputs as a basis for
generating READY.
READY remains active until either S1 or S0 are sampled
LOW, or the ready inputs are sampled as inactive.
5
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