TSM1N60S
N-Channel Power Enhancement Mode MOSFET
Pin assignment:
1. Gate
2. Drain
3. Source
V
DS
= 600V
I
D
= 0.3A
R
DS (on)
, Vgs @ 10V, Ids @ 0.3A = 11Ω
General Description
The TSM1N60s is used an advanced termination scheme to provide enhanced voltage-blocking capability without
degrading performance over time. In addition, this advanced MOSFET is designed to withstand high energy in avalanche
and commutation modes. The new energy efficient design also offers a drain- to-source diode with a fast recovery time.
Designed for high voltage, high speed switching applications in power supplies and converters, these devices are
particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer
additional and safety margin against unexpected voltage transients.
Features
Robust high voltage termination
Avalanche energy specified
Diode is characterized for use in bridge circuits
Source to Drain diode recovery time comparable to a
discrete fast recovery diode.
I
DSS
and V
DS(on)
specified at elevated temperature
Block Diagram
Ordering Information
Part No.
TSM1N60SCT B0
TSM1N60SCT A3
Packing
Bulk Pack
Ammo Pack
Package
TO-92
TO-92
Absolute Maximum Rating
(Ta = 25
o
C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Maximum Power Dissipation
Operating Junction Temperature
Operating Junction and Storage Temperature Range
Single Pulse Drain to Source Avalanche Energy
(V
DD
= 50V, V
GS
=10V, I
AS
=0.3A, L=115mH)
Ta = 25
o
C
o
Ta > 25 C
Symbol
V
DS
V
GS
I
D
I
DM
P
D
T
J
T
J
, T
STG
E
AS
Limit
600V
± 30
0.3
1.2
3
0.025
+150
- 55 to +150
50
Unit
V
V
A
A
W
o
W/ C
o
o
C
C
mJ
Thermal Performance
Parameter
Lead Temperature (1/8” from case)
Junction to Ambient Thermal Resistance (PCB mounted)
Note: Surface mounted on FR4 board t<=10sec.
Symbol
T
L
R
θja
Limit
10
50
Unit
S
o
C/W
TSM1N60S
1-4
2006/01 rev. A
Electrical Characteristics
Tj = 25
o
C, unless otherwise noted
Parameter
Static
Drain-Source Breakdown Voltage
Drain-Source On-State Resistance
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage
Forward Transconductance
Conditions
Symbol
Min
Typ
Max
Unit
V
GS
= 0V, I
D
= 250uA
V
GS
= 10V, I
D
= 0.3A
V
DS
= V
GS
, I
D
= 250uA
V
DS
= 600V, V
GS
= 0V
V
GS
= ± 30V, V
DS
= 0V
V
DS
≧50V,
I
D
= 0.3A
BV
DSS
R
DS(ON)
V
GS(TH)
I
DSS
I
GSS
g
fs
600
--
2.0
--
--
--
--
11
--
--
--
5
--
13
4.0
10
± 100
--
V
Ω
V
uA
nA
S
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= 25V, V
GS
= 0V,
f = 1.0MHz
V
DD
= 300V,
I
D
= 0.3A, V
GEN
= 10V,
R
G
= 4.7Ω
V
DS
= 480V, I
D
= 0.3A,
V
GS
= 10V
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
--
--
--
--
--
--
--
--
--
--
4.5
1.1
2.0
10
20
25
24
155
20
3
6.0
--
--
30
50
45
60
200
26
4
pF
nS
nC
Source-Drain Diode
Max. Diode Forward Current
Diode Forward Voltage
I
S
= 0.3A, V
GS
= 0V
Note: 1. pulse test: pulse width <=300uS, duty cycle <=2%
2. Negligible, Dominated by circuit inductance.
I
S
V
SD
--
--
--
--
0.3
1.4
A
V
TSM1N60S
2-4
2006/01 rev. A
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