November 2003
rev v1.0
ASM4SSTVF16859
DDR 13-Bit to 26-Bit Registered Buffer
LVCMOS level at a valid state since VREF may not be stable
during power-up.
To ensure that outputs are at a defined logic state before a
stable clock has been supplied, RESETB must be held at a
logic low level during power-up.
In the JEDEC defined Registered DDR DIMM application,
RESETB is specified to be asynchronous with respect to
CLK/CLKB; therefore, no timing relationship can be guaranteed
between the two signals. When entering a low-power standby
state, the register will be cleared and the outputs will be driven
to a logic low level quickly relative to the time to disable the
differential input receivers. This ensures there are no “glitches”
on any output. However, when coming out of low power
standby mode, the register will become active quickly relative to
the time taken to enable the differential input receivers. When
the data inputs are at a logic level low and the clock is stable
during the low-to-high transition of RESETB until the input
receivers are fully enabled, the design ensures that the outputs
will remain at a logic low level.
Features
•
•
•
•
Differential clock signals.
Meets SSTL_2 class II specifications on outputs.
Low voltage operation: V
DD
= 2.3V to 2.7V.
Available in 64-pin TSSOP, 64-pin TVSOP, and 56-pin
VFQFN packages.
Product Description
The ASM4SSTVF16859 is a universal 13/26 bit register (D F/F
based), designed for 2.3V to 2.7V V
DD
operation. The device
supports SSTL_2 I/O levels, and is fully compliant with the
JEDEC JC40, JC42.5 DDR I specifications covering PC1600,
PC 2100, PC2700, and PC3200 operational ranges. 13/26 bits
refers to 2Q outputs for each D input - designed for use in
Stacked Registered (stacked Memory Devices), Buffered DIMM
applications.
Data flow from D to Q is controlled by the differential clock
(CLK/CLKB) and a control signal (RESETB). The positive edge
of CLK is used to trigger the data transfer, and CLKB is used to
maintain sufficient noise margins, whereas RESETB input is
designed and intended for use at power-up.
The ASM4SSTVF16859 supports a low power standby mode of
operation. A logic level low at RESETB, assures that all internal
registers and outputs (Q) are reset to a logic low state, and that
all input receivers, data (D) buffers, and clock (CLK/CLKB) are
switched off. Note that RESETB should be supported with a
Applications
•
JEDEC and Non-JEDEC DDR Memory Modules
•Stacked or Planar configurations.
•Supports PC1600 - PC2100 - PC2700 - PC3200.
•
•
SSTL_2 I/O.
Provides a complete support solution for JEDEC JC42.5
DIMMs’ when used with the ASM5CVF857 Zero Delay
Buffer.
Block Diagram
CLK
CLKB
ASM4SSTVF16859
RESETB
D1
VREF
R
CLK
D1
Q1A
Q1B
To 12 other channels
Alliance Semiconductor
2575 Augustine Drive . Santa Clara, CA 95054 . Tel: 408.855.4900 . Fax: 408.855.4999 . www.alsc.com
Notice: The information in this document is subject to change without notice
November 2003
rev v1.0
ASM4SSTVF16859
Pin Configurations
Q13A
Q12A
Q11A
Q10A
Q9A
VDDQ
GND
Q8A
Q7A
Q6A
Q5A
Q4A
Q3A
Q2A
GND
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B
Q7B
Q6B
GND
VDDQ
Q5B
Q4B
Q3B
Q2B
Q1B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDQ
GND
D13
D12
VDD
VDDQ
GND
D11
D10
D9
GND
D8
D7
RESETB
GND
CLKB
CLK
VDDQ
VDD
VREF
D6
GND
D5
D4
D3
GND
VDDQ
VDD
D2
D1
GND
VDDQ
ASM4SSTVF16859
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ASM4SSTVF16859
42
41
40
39
38
37
36
35
34
33
32
31
30
29
64-pin TSSOP
6.10 mm body, 0.50 mm pitch
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-pin VFQFN (MLF2)
DDR 13-Bit to 26-Bit Registered Buffer
Notice: The information in this document is subject to change without notice
2 of 16
November 2003
rev v1.0
ASM4SSTVF16859
Pin Descriptions
64-pin TSSOP
Pin #
1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16,
17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
31, 32
7, 15, 26, 34, 39, 43, 50, 54, 58, 63
6, 18, 27, 33, 38, 47, 59, 64
35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57,
61, 62
48
49
37, 46, 60
51
45
Pin Name
Type
Description
Q (13:1)
GND
VDDQ
D(13:1)
CLK
CLKB
VDD
RESETB
VREF
O
P
P
I
I
I
P
I
I
Data output.
Ground to entire chip.
Output supply voltage, 2.5V nominal.
Data input.
Positive master clock input.
Negative master clock input.
Core supply voltage, 2.5V nominal.
Rest Active low.
Input reference voltage, 1.25V nominal.
56-pin MLF2
Pin #
1, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16,
18, 19, 20, 21, 22, 50, 51, 52, 53, 54, 56
37, 48
9, 17, 23, 27, 34, 44, 49, 55
24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47
35
36
26, 33, 45
38
32
-
Pin Name
Q (13:1)
GND
VDDQ
D(13:1)
CLK
CLKB
VDD
RESETB
VREF
Center Pad
Type
O
P
P
I
I
I
P
I
I
P
Description
Data output.
Ground to entire chip.
Output supply voltage, 2.5V nominal.
Data input.
Positive master clock input.
Negative master clock input.
Core supply voltage, 2.5V nominal.
Rest Active low.
Input reference voltage, 1.25V nominal.
Ground (VFQFN package only)
DDR 13-Bit to 26-Bit Registered Buffer
Notice: The information in this document is subject to change without notice
3 of 16
November 2003
rev v1.0
ASM4SSTVF16859
Truth Table
1
Inputs
RESETB
L
H
H
H
L or H
L or H
CLK
X or floating
CLKB
X or floating
D
X or floating
H
L
X
Q Outputs
Q
L
H
L
Q
02
Note:
1. H=High signal level, L=Low signal level, = transition from low to high, = transition from high to low, X = don’t care
2. Output level before the indicated steady state input conditions were established.
Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Input Voltage
1
Output Voltage
1,2
Input Clamp Current
Output Clamp Current
Continuous Output Current
VDD, VDDQ or GND current/pin
Package Thermal Impedance
3
Min
-65
-0.5
-0.5
-0.5
± 50
±50
±50
100
55
Max
+150
3.6
V
DD
+ 0.5
V
DD
+ 0.5
Unit
°C
V
V
V
mA
mA
mA
mA
°C/W
Note:
1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.
2. This current will flow only when the output is in the high state level V
0
> V
DDQ.
3. The package thermal impedance is calculated in accordance with JESD 51.
These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for prolonged
periods can affect device reliability.
DDR 13-Bit to 26-Bit Registered Buffer
Notice: The information in this document is subject to change without notice
4 of 16
November 2003
rev v1.0
ASM4SSTVF16859
Recomended Operating Conditions - DDRI / DDR333 (PC1600, PC2100, PC2700)
Guaranteed by design. Not 100% tested in production.
Parameter
V
DD
V
DDQ
V
REF
V
TT
V
I
V
IH(DC)
V
IH(AC)
V
IL(DC)
V
IL(AC)
V
IH
V
IL
V
ICR
V
ID
V
IX
I
OH
I
Ol
T
A
Supply voltage
I/O supply voltage
Reference voltage
Description
Min
2.3
2.3
1.15
V
REF
- 0.04
0
V
REF
+ 0.15
Data
Inputs
V
REF
+ 0.31
Typ
2.5
2.5
1.25
V
REF
Max
2.7
2.7
1.35
V
REF
+ 0.004
VDD
Unit
V
V
V
V
V
V
V
Termination voltage
Input voltage
DC input high voltage
AC input high voltage
DC input low voltage
AC input low voltage
Input high voltage level
RESETB
Input low voltage level
Common mode input range
Differential input voltage
Cross-point voltage of differential clock pair
High-level output current
Low-level output current
Operating free-air temperature
CLK
CLKB
V
REF
- 0.15
V
REF
- 0.31
1.7
0.7
0.97
0.36
(V
DDQ
/2) - 0.2
(V
DDQ
/2) +0.2
-20
20
0
70
1.53
V
V
V
V
V
V
V
mA
mA
°C
DDR 13-Bit to 26-Bit Registered Buffer
Notice: The information in this document is subject to change without notice
5 of 16
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