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74ACQ240 • 74ACTQ240 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs
July 1989
Revised November 1999
74ACQ240 • 74ACTQ240
Quiet Series Octal Buffer/Line Driver
with 3-STATE Outputs
General Description
The ACQ/ACTQ240 is an inverting octal buffer and line
driver designed to be employed as a memory address
driver, clock driver and bus oriented transmitter or receiver
which provides improved PC board density. The ACQ/
ACTQ utilizes Fairchild’s Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
Inverting 3-STATE outputs drive bus lines or buffer
memory address registers
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard ACT240
Ordering Code:
Order Number
74ACQ240SC
74ACQ240SJ
74ACQ240PC
74ACTQ240SC
74ACTQ240SJ
74ACTQ240QSC
Package Number
M20B
M20D
N20A
M20B
M20D
MQA20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC)JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
OE
1
, OE
2
I
0
–I
7
O
0
–O
7
Description
3-STATE Output Enable Inputs
Inputs
Outputs
FACT, Quiet Series, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010234
www.fairchildsemi.com
74ACQ240 • 74ACTQ240
Logic Symbol
IEEE/IEC
Truth Tables
Inputs
OE
1
L
L
H
Inputs
OE
2
L
L
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Outputs
I
n
L
H
X
(Pins 12, 14, 16, 18)
H
L
Z
Outputs
I
n
L
H
X
(Pins 3, 5, 7, 9)
H
L
Z
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2
74ACQ240 • 74ACTQ240
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
=
V
CC
+
0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
=
V
CC
+
0.5V
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
DC Latch-Up Source or
Sink Current
Junction Temperature (T
J
)
PDIP
140°C
±300
mA
±50
mA
−65°C
to
+150°C
±50
mA
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−20
mA
+20
mA
−0.5V
to V
CC
+
0.5V
−0.5V
to
+7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
ACQ
ACTQ
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
Minimum Input Edge Rate
∆V/∆t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate
∆V/∆t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
−40°C
to
+85°C
125 mV/ns
DC Electrical Characteristics for ACQ
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
IL
Maximum LOW Level
Input Voltage
V
OH
Minimum HIGH Level
Output Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
(Note 4)
I
OLD
I
OHD
I
CC
(Note 4)
I
OZ
Maximum Input
Leakage Current
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
5.5
±0.25
±2.5
µA
5.5
5.5
5.5
5.5
4.0
0.002
0.001
0.001
T
A
= +25°C
Typ
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
V
IN
=
V
IL
or V
IH
2.46
3.76
4.76
0.1
0.1
0.1
V
IN
=
V
IL
or V
IH
0.44
0.44
0.44
±1.0
75
−75
40.0
µA
mA
mA
µA
V
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA (Note 2)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
V
I
OUT
=
50
µA
V
I
OH
= −12
mA
I
OH
= −24
mA
I
OH
= −24
mA (Note 2)
V
I
OUT
= −50 µA
V
V
OUT
=
0.1V
or V
CC
−
0.1V
V
Units
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
3
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74ACQ240 • 74ACTQ240
DC Electrical Characteristics for ACQ
Symbol
V
OLP
V
OLV
V
IHD
V
ILD
Quiet Output
Maximum Dynamic V
OL
Quiet Output
Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
Parameter
V
CC
(V)
5.0
5.0
5.0
5.0
Typ
1.1
−0.6
3.1
1.9
(Continued)
T
A
= −40°C
to
+85°C
Guaranteed Limits
1.5
−1.2
3.5
1.5
V
V
V
V
Figure 1, Figure 2
(Note 5)(Note 6)
Figure 1, Figure 2
(Note 5)(Note 6)
(Note 5)(Note 7)
(Note 5)(Note 7)
T
A
= +25°C
Units
Conditions
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4:
I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 5:
Plastic DIP package.
Note 6:
Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 7:
Max number of data inputs (n) switching. (n
−1)
inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
V
IH
V
IL
V
OH
Parameter
Minimum HIGH Level
Input Voltage
Maximum LOW Level
Input Voltage
Minimum HIGH Level
Output Voltage
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
V
OLP
V
OLV
V
IHD
V
ILD
Maximum Input Leakage Current
Maximum 3-STATE
Leakage Current
Maximum I
CC
/Input
Minimum Dynamic
Output Current (Note 9)
Maximum Quiescent Supply Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Minimum
Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
5.0
1.1
−0.6
1.9
1.2
4.0
1.5
−1.2
2.2
0.8
0.6
0.001
0.001
T
A
= +25°C
Typ
1.5
1.5
1.5
1.5
4.49
5.49
2.0
0.8
0.8
4.4
5.4
3.86
4.86
0.1
0.1
0.36
0.36
±0.1
±0.25
2.0
T
A
= −40°C
to
+85°C
Guaranteed Limits
2.0
2.0
0.8
0.8
4.4
5.4
3.76
4.76
0.1
0.1
0.44
0.44
±1.0
±2.5
1.5
75
−75
40.0
µA
µA
mA
mA
mA
µA
V
V
V
V
V
Units
V
V
V
Conditions
V
OUT
=
0.1V
or V
CC
−
0.1V
V
OUT
=
0.1V
or V
CC
−
0.1V
I
OUT
= −50 µA
V
IN
=
V
IL
or V
IH
V
I
OH
= −24
mA
I
OH
= −24
mA (Note 8)
I
OUT
=
50
µA
V
IN
=
V
IL
or V
IH
V
I
OL
=
24 mA
I
OL
=
24 mA (Note 8)
V
I
=
V
CC
, GND
V
I
=
V
IL
, V
IH
V
O
=
V
CC
, GND
V
I
=
V
CC
−
2.1V
V
OLD
=
1.65V Max
V
OHD
=
3.85V Min
V
IN
=
V
CC
or GND
Figure 1, Figure 2
(Note 10)(Note 11)
Figure 1, Figure 2
(Note 10)(Note 11)
(Note 10)(Note 12)
(Note 10)(Note 12)
Note 8:
All outputs loaded; thresholds on input associated with output under test.
Note 9:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 10:
Plastic DIP package.
Note 11:
Max number of Data Inputs defined as (n). n−1 Data Inputs are driven 0V to 3V. One Data Input @ V
IN
=
GND.
Note 12:
Max number of Data Inputs (n) switching. (n−1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
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