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74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
January 2008
74AC14, 74ACT14
Hex Inverter with Schmitt Trigger Input
Features
■
I
CC
reduced by 50%
■
Outputs source/sink 24mA
■
74ACT14 has TTL-compatible inputs
General Description
The 74AC14 and 74ACT14 contain six inverter gates
each with a Schmitt trigger input. They are capable of
transforming slowly changing input signals into sharply
defined, jitter-free output signals. In addition, they have a
greater noise margin than conventional inverters.
The 74AC14 and 74ACT14 have hysteresis between the
positive-going and negative-going input thresholds (typi-
cally 1.0V) which is determined internally by transistor
ratios and is essentially insensitive to temperature and
supply voltage variations.
Ordering Information
Order
Number
74AC14SC
74AC14SJ
74AC14MTC
74AC14PC
74ACT14SC
74ACT14MTC
74ACT14PC
Package
Number
M14A
M14D
MTC14
N14A
M14A
MTC14
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1988 Fairchild Semiconductor Corporation
74AC14, 74ACT14 Rev. 1.7.1
www.fairchildsemi.com
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
I
n
O
n
Description
Inputs
Outputs
Function Table
Input
A
L
H
Output
O
H
L
©1988 Fairchild Semiconductor Corporation
74AC14, 74ACT14 Rev. 1.7.1
www.fairchildsemi.com
2
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
AC
ACT
V
I
V
O
T
A
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
©1988 Fairchild Semiconductor Corporation
74AC14, 74ACT14 Rev. 1.7.1
www.fairchildsemi.com
3
74AC14, 74ACT14 — Hex Inverter with Schmitt Trigger Input
DC Electrical Characteristics for AC
V
CC
Symbol
V
OH
T
A
=
+25°C
Conditions
I
OUT
=
–50µA
T
A
=
–40°C
to +85°C
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
2.2
3.2
3.9
0.5
0.9
1.1
1.2
1.4
1.6
0.3
0.4
0.5
75
–75
mA
mA
µA
V
V
V
µA
V
V
V
Parameter
Minimum HIGH Level
Output Voltage
(V)
3.0
4.5
5.5
3.0
4.5
5.5
Typ
2.99
4.49
5.49
Guaranteed Limits Units
2.9
4.4
5.4
2.56
3.86
4.86
I
OH
=
12mA
I
OH
=
24mA
I
OH
=
24mA
(1)
I
OUT
=
50µA
0.002
0.001
0.001
I
OL
=
12mA
I
OL
=
24mA
I
OL
=
24mA
(1)
V
I
=
V
CC
, GND
T
A
=
Worst Case
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
2.2
3.2
3.9
I
IN(3)
V
t+
Maximum Input Leakage
Current
Maximum Positive
Threshold
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
t–
Minimum Negative
Threshold
T
A
=
Worst Case
0.5
0.9
1.1
V
H(MAX)
Maximum Hysteresis
T
A
=
Worst Case
1.2
1.4
1.6
V
H(MIN)
Minimum Hysteresis
3.0
4.5
5.5
T
A
=
Worst Case
0.3
0.4
0.5
I
OLD
I
OHD
I
CC(3)
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
5.5
5.5
5.5
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
2.0
20.0
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
©1988 Fairchild Semiconductor Corporation
74AC14, 74ACT14 Rev. 1.7.1
www.fairchildsemi.com
4
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