Edition 2001-02-23
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
©
Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
C165UTAH
Revision History:
Previous Version:
Page
91
2001-02-23
Data Sheet, 10.00, DS1
1)
DS 2
Subjects (major changes since last revision)
Correction of the PEC Control Register:
The correct channel numbers are PEC channels 0 and 2.
The name of the corresponding register is PECXC2 and not PECXC1.
Correction: AS2 in was removed
Correction of the Parameter t14.
Improved formatting (text, figures, tables)
330
529
1)
All previous distributed versions are
preliminary.
They have been replaced by this version.
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
C165UTAH
Table of Contents
1
1.1
1.2
1.3
1.4
1.4.1
2
2.1
2.2
3
3.1
3.2
3.3
3.4
3.5
4
4.1
4.2
4.3
5
5.1
5.2
5.3
5.4
5.5
6
6.1
6.2
6.3
6.4
6.5
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Page
11
12
15
16
17
17
Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISDN NT and PBX Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
C165UTAH Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
C165UTAH Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . 19
Architectural Overview
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Organization
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal RAM and SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central Processor Unit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEC - Extension of Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
34
36
41
45
46
48
53
54
55
57
63
64
65
85
DMA - External PEC (EPEC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EPEC Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EPEC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
EPEC Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
EPEC Transfer Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Implementation of EPEC Interrupt Generation Unit . . . . . . . . . . . . . . . . . 101
Interrupt and Trap Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . . . .
Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
102
103
108
113
115
118
119
122
Data Sheet
2001-02-23
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