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74VHCT04A Hex Inverter
June 1997
Revised February 2005
74VHCT04A
Hex Inverter
General Description
The VHCT04A is an advanced high speed CMOS Inverter
fabricated with silicon gate CMOS technology. It achieves
the high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The internal circuit is composed of 3 stages including buffer
output, which provide high noise immunity and stable out-
put.
Protection circuits ensure that 0V to 7V can be applied to
the input pins without regard to the supply voltage and to
the output pins with V
CC
0V. These circuits prevent
device destruction due to mismatched supply and input/
output voltages. This device can be used to interface 3V to
5V systems and two supply systems such as battery
backup.
Features
■
High speed: t
PD
4.7 ns (typ) at T
A
2.0V, V
IL
25
q
C
0.8V
■
High noise immunity: V
IH
■
Power down protection is provided on all inputs and
outputs
■
Low noise: V
OLP
1.0V (max)
25
q
C
■
Low power dissipation:
I
CC
2
P
A (max) @ T
A
■
Pin and function compatible with 74HCT04
Ordering Code:
Order Number
74VHCT04AM
74VHCT04AMX_NL
(Note 1)
74VHCT04ASJ
74VHCT04AMTC
74VHCT04AMTCX_NL
(Note 1)
74VHCT04AN
74VHCT04ANX_NL
(Note 1)
Package
Number
M14A
M14A
M14D
MTC14
MTC14
N14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Used this number to order device.
© 2005 Fairchild Semiconductor Corporation
DS500024
www.fairchildsemi.com
74VHCT04A
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
A
n
O
n
Description
Inputs
Outputs
Truth Table
A
L
H
O
H
L
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2
74VHCT04A
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
(Note 3)
(Note 4)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
)
(Note 5)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
0.5V to 7.0V
20 mA
r
20 mA
r
25 mA
r
50 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 6)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
(Note 3)
(Note 4)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
5.0V
r
0.5V
0 ns/V
a
20 ns/V
Note 2:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3:
HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 4:
V
CC
0V.
Note 5:
V
OUT
GND, V
OUT
!
V
CC
(Outputs Active)
Note 6:
Unused inputs must be held HIGH or LOW. They may not float.
4.5V to
5.5V
0V to
5.5V
0V to V
CC
0V to 5.5V
40
q
C to
85
q
C
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
CC
I
CCT
I
OFF
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Leakage Current
Quiescent Supply Current
Maximum I
CC
/Input
Output Leakage Current
(Power Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
0
5.5
5.5
5.5
0.0
4.40
3.94
0.0
0.1
0.36
4.50
T
A
Min
2.0
2.0
0.8
0.8
4.40
3.80
0.1
0.44
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
2.0
2.0
0.8
0.8
Min
Units
V
V
V
V
V
V
V
IN
V
IN
V
IN
V
IN
V
IN
Conditions
V
IL
V
IH
I
OH
I
OH
I
OL
I
OL
50
P
A
8 mA
50
P
A
8 mA
r
0.1
2.0
1.35
0.5
r
1.0
20.0
1.50
5.0
P
A
P
A
mA
5.5V or GND
V
CC
or GND
3.4V
V
CC
or GND
Other Inputs
V
OUT
5.5V
P
A
Noise Characteristics
Symbol
V
OLP
(Note 7)
V
OLV
(Note 7)
V
IHD
(Note 7)
V
ILD
(Note 7)
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
Typ
0.8
25
q
C
Limits
1.0
1.0
2.0
0.8
Units
V
V
V
V
C
L
C
L
C
L
C
L
Conditions
50 pF
50 pF
50 pF
50 pF
0.8
Note 7:
Parameter guaranteed by design.
3
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74VHCT04A
AC Electrical Characteristics
Symbol
t
PHL
t
PLH
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance
Parameter
Propagation Delay
V
CC
(V)
5.0
r
0.5
Min
T
A
25
q
C
Typ
4.7
5.5
4
11
Max
6.7
7.7
10
T
A
40
q
C to
85
q
C
Max
7.5
8.5
10
1.0
1.0
Min
Units
ns
pF
pF
C
L
C
L
V
CC
Conditions
15 pF
50 pF
OPEN
(Note 8)
Note 8:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.) C
PD
* V
CC
* f
IN
I
CC
/6 (per gate).
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