through the burst sequence is controlled by the ADV input.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[3:0]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous chip selects (CE
1
, CE
2
, CE
3
) and an asyn-
chronous output enable (OE) provide for easy bank selection
and output three-state control. ADSP is ignored if CE
1
is
HIGH.
CY7C1347
GW is HIGH, then the write operation is controlled by BWE and
BW
[3:0]
signals. The CY7C1347 provides byte write capability
that is described in the write cycle description table. Asserting
the Byte Write Enable input (BWE) with the selected Byte
Write (BW
[3:0]
) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
0
–DQ
31
and DP inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
0
–DQ
31
and DPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE
1
, CE
2
, CE
3
are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW
[3:0]
) are asserted active to conduct a write to
the desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented to
A
0
–A
16
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is con-
ducted, the data presented to the DQ
0
–DQ
31
and DPs are
written into the corresponding address location in the RAM
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1347 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ
0
–DQ
31
and DP inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
0
–DQ
31
and DPs are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
is HIGH. The address presented to the address inputs
(A
0
–A
16
) is stored into the address advancement logic and the
address register while being presented to the memory core.
The corresponding data is allowed to propagate to the input of
the output registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Burst Sequences
The CY7C1347 provides a two-bit wraparound counter, fed by
A
0
and A
1
, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
0
–A
16
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[0:3]
) and ADV inputs are ig-
nored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
0
–DQ
31
and DP inputs are written
into the corresponding address location in the RAM core. If
Interleaved Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
00
11
10
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
10
01
00
4
PRELIMINARY
Linear Burst Sequence
First
Address
Ax+1, Ax
00
01
10
11
Second
Address
Ax+1, Ax
01
10
11
00
Third
Address
Ax+1, Ax
10
11
00
01
Fourth
Address
Ax+1, Ax
11
00
01
10
Sleep Mode
CY7C1347
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE
1
, CE
2
, CE
3
, ADSP, and ADSC must remain inactive for the
duration of t
ZZREC
after the ZZ input returns LOW.
Cycle Description Table
[1, 2, 3]
Cycle Description
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Deselected Cycle, Power-down
Snooze Mode, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
ADD
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE
1
H
L
L
L
X
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE
3
X
X
H
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CE
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSP
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
Note:
1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS
[3:0].
Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a don't care for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active
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