The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 12 ns with output enable access times (t
OE
) of 6 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank
systems.
When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume I
SB
power. If the bus is static, then full standby power is reached (I
SB1
).
A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0
through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2).
To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE)
or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable
is inactive, or write enable is active, output drivers stay in high-impedance mode.
Absolute maximum ratings
Parameter
Voltage on V
CC
relative to GND
Voltage on any pin relative to GND
Power dissipation
Storage temperature (plastic)
Ambient temperature with V
CC
applied
DC current into outputs (low)
Note:
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Symbol
V
t1
V
t2
P
D
T
stg
T
bias
I
OUT
Min
–0.50
–0.50
–
–55
–55
–
Max
+7.0
V
CC
+0.50
1.25
+125
+125
50
Unit
V
V
W
°C
°C
mA
Truth table
CE1
H
X
L
L
L
CE2
X
L
H
H
H
WE
X
X
H
H
L
OE
X
X
H
L
X
Data
High Z
High Z
High Z
D
OUT
D
IN
Mode
Standby (I
SB
, I
SB1
)
Standby (I
SB
, I
SB1
)
Output disable (I
CC
)
Read (I
CC
)
Write (
ICC
)
Key: X = don’t care, L = low, H = high.
12/5/06, v. 1.0
Alliance Memory
P. 2 of 9
AS7C1024C
®
Recommended operating conditions
Parameter
Supply Voltage
Input Voltage
Ambient operating temperature (Industrial)
Note:
1 V
IL
min = -1.5V for pulse width less than 10ns, once per cycle.
Symbol
V
CC
V
IH
V
IL
(1)
T
A
Min
4.5
2.2
–0.5
(1)
–40
Nominal
5.0
-
–
–
Max
5.5
V
CC
+ 0.5
0.8
85
Unit
V
V
V
°C
DC operating characteristics (over the operating range)
1
AS7C1024C-12
Parameter
Input leakage current
Output leakage current
Symbol
|I
LI
|
|I
LO
|
I
CC
I
SB
Test conditions
V
CC
= Max, V
IN
= GND to V
CC
V
CC
= Max, CE1 = V
IH
or
CE2 = V
IL
, V
OUT
= GND to V
CC
V
CC
= Max, CE1
≤
V
IL
,
CE2
≥
V
IH
, f = f
Max
,
I
OUT
= 0 mA
V
CC
= Max, CE1
≥
V
IH
and/or
CE2
≤
V
IL
, f = f
Max
V
CC
= Max, CE1
≥
V
CC
–0.2V
and/or CE2
≤
0.2V
V
IN
≤
0.2V or
V
IN
≥
V
CC
– 0.2V, f = 0
I
OL
= 8 mA, V
CC
= Min
I
OH
= –4 mA, V
CC
= Min
Min
–
–
Max
5
5
Unit
μA
μA
Operating power supply current
–
160
mA
–
40
mA
Standby power supply current
1
I
SB1
–
10
mA
Output voltage
V
OL
V
OH
–
2.4
0.4
–
V
V
Capacitance (
f = 1 MHz, T
a
= 25
o
C, V
CC
= NOMINAL
)
2
Parameter
Input capacitance
I/O capacitance
Note:
This parameter is guaranteed by device characterization, but is not production tested.
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