DATASHEET
CLOCK SYNTHESIZER FOR PDA
Description
The ICS620A-06 generates four high-quality,
high-frequency clock outputs. It is a low-power, low-jitter
clock synthesizer developed for PDA (personal digital
assistant) applications, to replace multiple crystals and
crystal oscillators. This chip offers all of the standard clocks
required for a PDA. This chip uses ICS’ proprietary mix of
analog and digital Phase-Locked Loop (PLL) technology.
I
2
C bus programming is used to change the CPU and the
USB clocks in circuit. In addition, the I
2
C serial bus allows
the individual clock outputs to be enabled or disabled
through software to offer further power savings.
ICS620A-06
Features
•
Extremely low operating current (5 mA)
•
Input crystal or clock frequency of 24 MHz
•
I
2
C programmable processor clock frequency for CPU
and USB
•
•
•
•
•
•
•
•
•
Fixed 24.576 MHz and 3.68 MHz outputs
Individual clock enable/disable control through I
2
C
Individual PLL and chip power down features
Operating voltage of 1.8 V core
Output voltage of either 1.8 V or 2.5 V
Advanced, low-power CMOS process
Packaged in 32-pin QFN (RoHS compliant)
Industrial temperature range available (-40 to +85°C)
Chip Power-down
Block Diagram
VDD
4
VDDO
5
SCLK
SDATA
I
2
C
Control
Logic
PLL1
CPU
X1
24 MHz
clock or
crystal input X2
Optional tuning
capacitors
Crystal
Oscillator/
Clock
Buffer
24.576M
PLL2
3.68M
Divider
USB
7
GND
PD
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PDA
1
ICS620A-06
REV C 061406
CONFIDENTIAL (DELETE IF NOT NEEDED)
ICS620A-06
CLOCK SYNTHESIZER FOR PDA
CLOCK SYNTHESIZER
Pin Assignment
GND
GND
VDD
GND
NC
PD
X1
X2
Table 1
Clock
CPU
USB
Available Frequencies (MHz)
13, 12, 10, 8, 6, 4, 2,1
6, 12, 24,
NC
GND
USB
VDDO_USB
VDDO_CPU
CPU
GND
NC
1
25
VDD
VDD
24.576M
VDDO_24.576M
VDDO_3.686M
3.686M
NC
17
9
VDD_DIGITAL
GND
VDD
SDATA
GND
NC
32-pin QFN
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SCLK
Pin
Name
NC
GND
USB
VDDO_USB
VDDO_CPU
CPU
GND
NC
NC
GND
VDD
SCLK
SDATA
GND
NC
NC
VDD_DIGITAL
NC
3.6864M
NC
NC
Pin
Type
—
Power
Output
Power
Power
Output
Power
—
—
Power
Power
Input
Input
Power
—
—
Power
—
Output
Connect to ground.
Pin Description
No connect. Do not connect this pin to anything.
USB Clock Selection per Table 1 and Table 2 Byte 2.
Output voltage supply for USB clock, 1.8 V or 2.5 V.
Output voltage supply for CPU clock, 1.8 V or 2.5 V.
Processor clock output. Selection per Table 1 and Table 2 Byte 1.
Connect to ground.
No connect. Do not connect this pin to anything.
No connect. Do not connect this pin to anything.
Connect to ground.
Connect to +1.8 V.
I
2
C bus clock pin. Internal pull-up resistor. See note1.
I
2
C bus data pin. Internal pull-up resistor. See note1.
Connect to ground.
No connect. Do not connect this pin to anything.
No connect. Do not connect this pin to anything.
Voltage supply for PD, SCLK, and SDATA pins.
No connect. Do not connect this pin to anything.
3.6864MHz clock output.
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PDA
2
ICS620A-06
REV C 061406
ICS620A-06
CLOCK SYNTHESIZER FOR PDA
CLOCK SYNTHESIZER
Pin
Number
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin
Name
VDDO_3.686M
VDDO_24.576M
24.576M
VDD
VDD
GND
GND
GND
PD
VDD
X2
X1
NC
Pin
Type
Power
Power
Output
Power
Power
Power
Power
Power
Input
Power
Output
Input
—
Pin Description
Output voltage supply for 3.686 MHz clock – 1.8 V or 2.5 V.
Output voltage supply for 24.576 MHz clock – 1.8 V or 2.5 V.
24.576 MHz clock for audio.
Connect to +1.8 V.
Connect to +1.8 V.
Connect to ground.
Connect to ground.
Connect to ground.
PD =1, chip operates normally. PD = 0, chip powers down. Internal
pull-up. This pin over rides the PLL power down feature from I2C bus.
Connect to +1.8 V.
Connect to 24 MHz crystal. No connect if clock input on pin 20.
Crystal connection. Connect to 24 MHz crystal or clock input.
No connect. Do not connect this pin to anything.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS620A-06 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
capacitors must be connected from each of the pins X1 and
X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-6
pF)*2. In this equation, C
L
= crystal load capacitance in pF.
Example: For a crystal with a 16 pF load capacitance, each
crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) The 0.01µF decoupling capacitors should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitors and VDD pins. The PCB trace to VDD pins
should be kept as short as possible, as should the PCB
trace to the ground via.
2) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, the 33Ω series termination resistor (if
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PDA
3
ICS620A-06
REV C 061406
ICS620A-06
CLOCK SYNTHESIZER FOR PDA
CLOCK SYNTHESIZER
needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the
ICS620A-06. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used
by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS620A-06. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs
All Outputs
Storage Temperature
Junction Temperature
Soldering Temperature
ESD (HBM)
MSL (Moisture Sensitivity Level)
-0.5 V to 3.6 V
Rating
-0.5 V to VDD+0.5 V
-0.5 V to 2.5 V+0.5 V
-65 to +150°C
125°C
260°C
2000 V min.
3
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Output Power Supply Voltage (with respect to GND)
Power Supply Voltage (with respect to GND)
Min.
0
-40
+1.71
+1.71
Typ.
Max.
+70
+85
+2.625
+1.89
Units
°C
°C
V
V
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PDA
4
ICS620A-06
REV C 061406
ICS620A-06
CLOCK SYNTHESIZER FOR PDA
CLOCK SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise,
VDD = 1.8 V ±5%, VDDO = 2.5 V ±5% ,
T
A
= 0 to +70°C or -40 to +85°C
Parameter
Operating Voltage
Output Voltage
Supply Current
Symbol
VDD
VDDO
IDD
Conditions
Min.
1.71
1.71
Typ.
Max.
1.89
2.625
Units
V
V
mA
mA
µa
V
No load, VDD = 1.8 V,
VDDO = 1.8 V
No load, VDD = 1.8 V,
VDDO = 2.5 V
4.5
5.5
50
0.7VDD
0.3VDD
Standby Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance, inputs
Load Capacitance, X1 and
X2
Internal Pull-up Resistor
Internal Pull-down Resistor
IDD
Standby
V
IH
V
IL
V
OH
V
OL
C
IN
C
L
R
PU
R
PD
No load, PD = 0, VDD
= 1.8 V, VDDO = 2.5 V
V
V
V
pF
pF
kΩ
kΩ
I
OH
= -2 mA
I
OL
= +2 mA
0.8VDDO
0.2VDDO
5
5
100
40
250
250
No internal load
capacitance
AC Electrical Characteristics
Unless stated otherwise,
VDDO = 2.5 V ±5%, C
L
= 5 pF,
T
A
= 0 to +70°C or -40 to +85°C
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Output Impedance
Output Clock Duty Cycle
Short Term Jitter
Long Term Jitter
Power-up Time
Output Enable Time
Output Disable Time
Symbol
f
IN
t
OR
t
OF
R
O
Conditions
20% to 80%, Note 1
80% to 20%, Note 1
VO=VDDO/2
VDDO/2, Note 1
Cycle-to-Cycle
n=1000
Min.
0.7
0.7
33
40
Typ.
24
1.5
1.5
46
50
150
1.5
Max. Units
MHz
2.2
2.2
68
60
250
750
3
10
10
ns
ns
Ω
%
ps
ps
ms
ns
ns
t
PU
From minimum VDD
to outputs stable
Note 1: Measured with a 5 pF load.
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PDA
5
ICS620A-06
REV C 061406
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