DATASHEET
LOW PHASE NOISE CLOCK MULTIPLIER
Description
The ICS601-21 is a low-cost, low phase noise, high
performance clock synthesizer for applications which
require low phase noise and low jitter. It is IDT’s lowest
phase noise multiplier. Using IDT’s patented analog and
digital Phase Locked Loop (PLL) techniques, the chip
accepts a crystal or clock input, and produces output clocks
up to 230 MHz at 3.3 V.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
ICS601-21
Features
•
Fully integrated PLL, no external loop filter required
•
Differential 3.3 V LVPECL outputs
•
Uses fundamental crystal or clock
— Crystal input frequency: 10 to 27MHz
— Clock input: 10 to 38MHz (mulitply by 6)
10 to 31MHz (all other multiply settings)
•
•
•
•
•
•
•
•
Output clocks up to 230 MHz at 3.3 V
Low phase noise: -122 dBc/Hz at 10 kHz
Low jitter - 15 ps one sigma typ.
Powerdown mode lowers power consumption
Packaged in 16-pin TSSOP, Pb-free
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Commercial temperature range available
Block Diagram
VDD
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
CLK
nCLK
X1/ICLK
Crystal or
clock input
X2
ROM Based
Multipliers
Crystal
Oscillator
VCO
Divide
4
S2:0
GND
IDT®
LOW PHASE NOISE CLOCK MULTIPLIER
1
ICS601-21
REV J 121412
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
X1
VD D
VD D
VD D
GND
VD D
GND
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
GND
C LK
nC LK
VD D
S0
S1
S2
Multiplier Select Table
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Multiplier
x1
x2
x3
x4
x5
x6
x8
x16
16 Pin (173 m il) TSSOP
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Number
1
2-4
5
6
7-8
9
10
11
12
13
14
15
16
Pin
Name
X1
VDD
GND
VDD
GND
S2
S1
S0
VDD
nCLK
CLK
GND
X2
Pin
Type
XI
Power
Power
Power
Power
Input
Input
Input
Power
Output
Output
Power
XO
Pin Description
Crystal or clock input. Connect to a fundamental parallel mode crystal or clock
input. See electrical tables for input frequenct ranges.
Connect to +3.3 V.
Connect to ground.
Connect to +3.3 V.
Connect to ground.
Select pin 2. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Select pin 0. Internal pull-up resistor.
Connect to +3.3 V.
Inverted differential clock output.
Differential clock output.
Connect to ground.
Crystal connection. Connect to a fundamental parallel mode crystal or leave
unconnected for clock input. See electrical tables for input frequenct ranges.
IDT®
LOW PHASE NOISE CLOCK MULTIPLIER
2
ICS601-21
REV J 121412
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
External Components
The ICS601-21 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01F and 0.1
F
should be connected between VDD and GND, as close to the part as possible. A 50
terminating resistor should be used on each clock output. (See termination diagram on page 5). The crystal must
be connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do not
use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1 to ground
and X2 to ground. In general, the value of these capacitors is given by the following equation, where CL is the
crystal load capacitance: Crystal caps (pF) = (CL-5) x 2. So for a crystal with 16 pF load capacitance, two 22 pF
caps can be used. For any given board layout, IDT can measure the board capacitance and recommend the exact
capacitance value to use.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-21. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial version
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70
C
-65 to +150
C
125
C
260
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+3.6
Units
C
V
DC Electrical Characteristics
VDD=3.3 V ±0.3V,
Ambient temperature 0 to +70C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Symbol
VDD
V
IH
V
IL
Conditions
X1/ICLK pin only
X1/ICLK pin only
Min.
3.0
VDD/2+1
Typ.
Max.
3.6
VDD/2-1
Units
V
V
V
IDT®
LOW PHASE NOISE CLOCK MULTIPLIER
3
ICS601-21
REV J 121412
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
DC Electrical Characteristics
(continued)
Parameter
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Voltage Swing
Operating Supply Current
Input Capacitance
On Chip Pull-up Resistor
Symbol
V
IH
V
IL
V
OH
V
OL
V
swing
IDD
C
IN
R
PU
Conditions
Input select pins
Input select pins
Note 1
Note 1
Peak to Peak
Note 1, 125 MHz
Input select pins
Input select pins
Min.
2
VDD-1.4
VDD-2.0
0.6
Typ.
Max.
VDD
0.8
VDD-1.0
VDD-1.7
0.95
Units
V
V
V
V
V
mA
pF
k
30
5
510
45
Note 1: Outputs terminated with 50 to VDD-2V
AC Electrical Characteristics
VDD = 3.3 V ±0.3V,
Ambient Temperature 0 to +70 C
Parameter
Crystal Input Frequency
Clock Input Frequency
Symbol
Fin
Fin
Note 2
Conditions
Note 2, “Multiply by 6” setting
Note 2, excluding “Multiply by 6”
setting
Min.
10
10
10
10
Typ.
Max.
27
38
31
230
Units
MHz
MHz
MHz
MHz
ps
ps
%
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Output Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter, short
term, 125 MHz
Maximum Jitter, one sigma,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
Phase Noise, relative to carrier,
125 MHz (x5)
t
OR
t
OF
20% to 80%, no load
80% to 20%, no load
at VDD/2
No load
No load
100 Hz offset
1 kHz
10 kHz offset
100 kHz offset
600
900
45
50
±50
12
-90
-116
-118
-115
-94
-120
-122
-119
900
1200
55
±75
20
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x, maximum input
frequency is 13.75 MHz).
IDT®
LOW PHASE NOISE CLOCK MULTIPLIER
4
ICS601-21
REV J 121412
ICS601-21
LOW PHASE NOISE CLOCK MULTIPLIER
CLOCK MULTIPLIER
Parameter Measurement Information
V
D D
= 3.3V
V
D D
= 3.3V
Z = 50
Qx
Z = 50
SCOPE
Qx
LV P E C L
Z = 50
nQ x
50
LV P E C L
Z = 50
nQ x
50
G N D =0V
50
G N D =0V
50
V
D D
-2V = 1.3V
3.3V LV P E C L D river Term ination
3.3V O utput Load A C Test C ircuit
V
OH
nFOUT
FOUT
t
cycle(n)
t
cycle(n+1)
HISTOGRAM
Mean Period
(First edge after trigger)
V
REF
V
OL
Reference Point
t
jit(cc) =
t
cycle(n) -
t
cycle(n+1)
1000 Cycles
1s contains 68.26% of all measurements
2s contains 95.4% of all measurements
3s contains 99.73% of all measurements
4s contains 99.99366% of all measurements
6s contains (100-1.973x10
-7
)% of all measurements
CYCLE-TO-CYCLE JITTER
Period Jitter
nFOUT
80%
80%
V
SWING
FOUT
Pulse Width
t
PERIOD
ODC =
t
PW
t
PERIOD
Clock
Outputs
20%
20%
t
OR
t
OF
O
UTPUT
D
UTY
C
YCLE AND
t
PERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
IDT®
LOW PHASE NOISE CLOCK MULTIPLIER
5
ICS601-21
REV J 121412
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
