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74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
January 2000
Revised October 2001
74LVT16952 • 74LVTH16952
Low Voltage 16-Bit Registered Transceiver
with 3-STATE Outputs
General Description
The LVT16952 and LVTH16952 are 16-bit registered
transceivers. Two 8-bit back to back registers store data
flowing in both directions between two bidirectional buses.
Separate clock, clock enable, and output enable signals
are provided for each register.
The LVTH16952 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The registered transceiver is designed for low-voltage
(3.3V) V
CC
applications, but with the capability to provide a
TTL interface to a 5V environment.
The LVT16952 and LVTH16952 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining low power dissi-
pation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16952)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
−
32 mA/
+
64 mA
s
Functionally compatible with the 74 series 16952
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Order Number
74LVT16952MEA
(Preliminary)
74LVT16952MTD
(Preliminary)
74LVTH16952MEA
74LVTH16952MTD
Package Number
MS56A
MTD56
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2001 Fairchild Semiconductor Corporation
DS500103
www.fairchildsemi.com
74LVT16952 • 74LVTH16952
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
16
B
0
–B
16
CPAB
n
, CPBA
n
CEA
n
, CEB
n
OEAB
n
, OEBA
n
Description
Data Register A Inputs
B-Register 3-STATE Outputs
Data Register B Inputs
A-Register 3-STATE Outputs
Clock Pulse Inputs
Clock Enable
Output Enable Inputs
Truth Table
(Note 1)
Inputs
A
n
CPAB
n
CEA
n
OEAB
n
X
X
L
L
H
H
X
X
X
X
X
H
H
L
L
L
L
X
X
X
X
L
H
L
H
L
H
L
L
H
H
Internal Register Output
Value
NC
NC
L
L
H
H
NC
NC
NC
NC
B
n
B
0
Z
L
Z
H
Z
B
0
B
0
Z
Z
L
H
L
H
X
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
Output High Impedance
=
LOW-to-HIGH Transition.
NC
=
No Change (state established by last valid CP)
B
0
=
State established by last valid CP
Note 1:
A to B data flow shown; B to A flow control is the same, but used
OEBA
n
, CPBA
n
and CEB
n
.
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2
74LVT16952 • 74LVTH16952
Logic Diagram
Note:
n
for either byte 1 or byte 2.
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LVT16952 • 74LVTH16952
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
<
GND
V
O
<
GND
V
O
>
V
CC
V
O
>
V
CC
Output at HIGH State
Output at LOW State
V
V
mA
mA
mA
mA
mA
−
0.5 to
+
4.6
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
0.5 to
+
7.0
−
50
−
50
64
128
±
64
±
128
−
65 to
+
150
°
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
−
32
64
−
40
0
+
85
10
°
C
ns/V
∆
t/
∆
V
Note 2:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3:
I
O
Absolute Maximum Rating must be observed.
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