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74LVT16646 • 74LVTH16646 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
January 2000
Revised October 2001
74LVT16646 • 74LVTH16646
Low Voltage 16-Bit Transceiver/Register
with 3-STATE Outputs
General Description
The LVT16646 and LVTH16646 contains sixteen non-
inverting bidirectional registered bus transceivers providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Each byte has sepa-
rate control inputs which can be shorted together for full
16-bit operation. The DIR inputs determine the direction of
data flow through the device. The CPAB and CPBA inputs
load data into the registers on the LOW-to-HIGH transition
(see Functional Description).
The LVTH16646 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These transceivers are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT16646 and
LVTH16646 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16646)
s
Also available without bushold feature (74LVT16646)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides
glitch-free bus loading
s
Outputs source/sink
−
32 mA/
+
64 mA
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human-body model
>
2000V
Machine model
>
200V
Charged-device model
>
1000V
Ordering Code:
Order Number
74LVT16646MEA
(Preliminary)
74LVT16646MTD
(Preliminary)
74LVTH16646MEA
74LVTH16646MTD
Package Number
MS56A
MTD56
MS56A
MTD56
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation
DS012023
www.fairchildsemi.com
74LVT16646 • 74LVTH16646
Connection Diagram
Pin Descriptions
Pin Names
A
0
–A
15
B
0
–B
15
CPAB
n
, CPBA
n
SAB
n
, SBA
n
OE
1
, OE
2
DIR
n
Description
Data Register A Inputs/3-STATE Outputs
Data Register B Inputs/3-STATE Outputs
Clock Pulse Inputs
Select Inputs
Output Enable Inputs
Direction Control Inputs
Truth Table
(Note 1)
Inputs
OE
1
H
H
H
L
L
L
L
L
L
L
L
DIR
1
X
X
X
H
H
H
H
L
L
L
L
CPAB
1
CPBA
1
SAB
1
H or L
X
SBA
1
X
X
X
X
X
X
X
L
L
H
H
Output
Input
Input
Input
Input
Data I/O
A
0–7
B
0–7
Isolation
Clock A
n
Data into A Register
Clock B
n
Data Into B Register
A
n
to B
n
—Real Time (Transparent Mode)
Output Clock A
n
Data to A Register
A Register to B
n
(Stored Mode)
Clock A
n
Data into A Register and Output to B
n
B
n
to A
n
—Real Time (Transparent Mode)
Clock B
n
Data into B Register
B Register to A
n
(Stored Mode)
Clock B
n
into B Register and Output to A
n
Output Operation Mode
X
X
X
X
X
H or L
X
X
X
L
L
H
H
X
X
X
X
X
X
X
X
X
H or L
H or L
H
=
HIGH Voltage Level
X
=
Immaterial
L
=
LOW Voltage Level
=
LOW-to-HIGH Transition.
X
Note 1:
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e.,
data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control
pins.
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2
74LVT16646 • 74LVTH16646
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both. The select (SAB
n
, SBA
n
) controls can multiplex
stored and real-time. The examples shown below demon-
strate the four fundamental bus-management functions
that can be performed.
The direction control (DIR
n
) determines which bus will
receive data when OE
n
is LOW. In the isolation mode (OE
n
HIGH), A data may be stored in one register and/or B data
may be stored in the other register. When an output func-
tion is disabled, the input function is still enabled and may
be used to store and transmit data. Only one of the two
busses, A or B, may be driven at a time.
Real-Time Transfer
Bus B to Bus A
Real-Time Transfer
Bus A to Bus B
OE DIR CPAB CPBA SAB SBA
L
L
X
X
X
L
OE DIR CPAB CPBA SAB SBA
L
H
X
X
L
X
Transfer Storage
Data to A or B
Storage
OE DIR CPAB CPBA SAB SBA
OE DIR CPAB CPBA SAB SBA
L
L
L
H
X
H or L
H or L
X
X
H
H
X
L
L
H
H
H
L
X
X
X
X
L
X
X
X
X
L
X
X
X
X
3
www.fairchildsemi.com
74LVT16646 • 74LVTH16646
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
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