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74LVTH162373 Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs and 25: Series Resistors in the
Outputs
October 2000
Revised June 2005
74LVTH162373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs and
25: Series Resistors in the Outputs
General Description
The LVTH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
The LVTH162373 is designed with equivalent 25
:
series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
The LVTH162373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162373 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs include equivalent series resistance of 25
:
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Functionally compatible with the 74 series 16373
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVTH162373MEA
74LVTH162373MEX
(Note 1)
74LVTH162373MTD
74LVTH162373MTX
(Note 1)
Package
Number
MS48A
MS48A
MTD48
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBES]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1:
Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation
DS500354
www.fairchildsemi.com
74LVTH162373
Connection Diagram
Pin Descriptions
Pin Names
OE
n
LE
n
I
0
–I
15
O
0
–O
15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
3-STATE Outputs
Truth Tables
Inputs
LE
1
X
H
H
L
OE
1
H
L
L
L
Inputs
LE
2
X
H
H
L
H
L
X
Z
O
o
Outputs
I
0
–I
7
X
L
H
X
O
0
–O
7
Z
L
H
O
o
Outputs
I
8
–I
15
X
L
H
X
O
8
–O
15
Z
L
H
O
o
OE
2
H
L
L
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
HIGH Impedance
Previous output prior to HIGH-to-LOW transition of LE
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each
byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation.
The following description applies to each byte. When the Latch Enable (LE
n
) input is HIGH, data on the D
n
enters the
latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes.
When LE
n
is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW
transition of LE
n
. The 3-STATE standard outputs are controlled by the Output Enable (OE
n
) input. When OE
n
is LOW, the
standard outputs are in the 2-state mode. When OE
n
is HIGH, the standard outputs are in the high impedance mode but
this does not interfere with entering new data into the latches.
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2
74LVTH162373
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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74LVTH162373
Absolute Maximum Ratings
(Note 2)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 3)
V
I
GND
V
O
GND
V
O
!
V
CC
V
O
!
V
CC
Output at HIGH State
Output at LOW State
V
mA
mA
mA
mA
mA
0.5 to
4.6
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
50
50
64
128
r
64
r
128
65 to
150
q
C
Recommended Operating Conditions
Symbol
V
CC
V
I
I
OH
I
OL
T
A
Supply Voltage
Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
Parameter
Min
2.7
0
Max
3.6
5.5
Units
V
V
mA
mA
12
12
40
0
85
10
q
C
ns/V
'
t/
'
V
Note 2:
Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 3:
I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
V
OL
I
I(HOLD)
I
I(OD)
I
I
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Bushold Input Minimum Drive
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZH
I
OZH
I
CCH
I
CCL
I
CCZ
Power Off Leakage Current
Power Up/Down 3-STATE
Output Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7–3.6
3.0
2.7
3.0
3.0
3.0
75
V
CC
0.2
2.0
0.2
0.8
2.0
0.8
T
A
40
q
C to
85
q
C
Max
Min
Units
V
V
V
V
V
I
I
Conditions
1.2
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OL
I
OL
V
I
V
I
100
P
A
12mA
100
P
A
12 mA
0.8V
2.0V
75
500
P
A
P
A
10
(Note 4)
(Note 5)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
3.0V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
10
0.19
5
0.19
P
A
P
A
P
A
P
A
P
A
mA
mA
mA
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
V
CC
V
O
d
5.5V
Outputs HIGH
Outputs LOW
Outputs Disabled
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