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74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
February 2008
74LVT373, 74LVTH373
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
■
Input and output interface capability to systems at
■
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfy-
ing the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in a high
impedance state.
The LVTH373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and
LVTH373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
■
■
■
■
■
5V V
CC
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH373),
also available without bushold feature (74LVT373)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32 mA/+64 mA
Functionally compatible with the 74 series 373
ESD performance:
– Human-body model
>
2000V
– Machine model
>
200V
– Charged-device model
>
1000V
Ordering Information
Order Number
74LVT373WM
74LVT373SJ
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
Package
Number
M20B
M20D
MTC20
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Truth Table
Functional Description
The LVT373 and LVTH373 contain eight D-type latches
with 3-STATE standard outputs. When the Latch Enable
(LE) input is HIGH, data on the D
n
inputs enters the
latches. In this condition the latches are transparent, i.e.,
a latch output will change state each time its D input
changes. When LE is LOW, the latches store the infor-
mation that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard out-
puts are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but
this does not interfere with entering new data into the
latches.
Inputs
LE
X
H
H
L
Outputs
D
n
X
L
H
X
OE
H
L
L
L
O
n
Z
L
H
O
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition
of Latch Enable
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
2
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
3
74LVT373, 74LVTH373 — Low Voltage Octal Transparent Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
I
V
O
Supply Voltage
DC Input Voltage
DC Output Voltage
Output in 3-STATE
Parameter
Rating
–0.5V to +4.6V
–0.5V to +7.0V
–0.5V to +7.0V
–0.5V to +7.0V
–50mA
–50mA
64mA
128mA
±64mA
±128mA
–65°C to +150°C
Output in HIGH or LOW State
(1)
I
IK
I
OK
I
O
DC Input Diode Current, V
I
<
GND
DC Output Diode Current, V
O
<
GND
DC Output Current, V
O
>
V
CC
Output at HIGH State
Output at LOW State
I
CC
I
GND
T
STG
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Note:
1. I
O
Absolute Maximum Rating must be observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
I
I
OH
I
OL
T
A
∆
t /
∆
V
Supply Voltage
Input Voltage
Parameter
Min
2.7
0
Max
3.6
5.5
–32
64
Units
V
V
mA
mA
°C
ns/V
HIGH-Level Output Current
LOW-Level Output Current
Free-Air Operating Temperature
Input Edge Rate, V
IN
=
0.8V–2.0V, V
CC
=
3.0V
–40
0
85
10
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
www.fairchildsemi.com
4
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