74LCXR162245 Low Voltage 16-Bit Bidirectional Transceiver with 5V Tolerant Inputs/Outputs and 26
:
Series
Resistors in the Outputs
August 1998
Revised June 2005
74LCXR162245
Low Voltage 16-Bit Bidirectional Transceiver
with 5V Tolerant Inputs/Outputs
and 26: Series Resistors in the Outputs
General Description
The LCXR162245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is designed for low volt-
age (2.5V or 3.3V) V
CC
applications with capability of inter-
facing to a 5V signal environment. The device is byte
controlled. Each byte has separate control inputs which
could be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
In addition, all A and B outputs include equivalent 26
:
(nominal) series resistors to reduce overshoot and under-
shoot and are designed to sink/source up to 12 mA at
V
CC
3.0V.
The LCXR162245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V–3.6V V
CC
specifications provided
s
A and B side outputs have equivalent 26
:
series
resistors
s
5.3 ns t
PD
max (V
CC
3.3V), 20
P
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Flow through pinout
s
Implements proprietary noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1:
To ensure the high-impedance state during power up or down OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number
74LCXR162245MEA
74LCXR162245MEX
74LCXR162245MTD
74LCXR162245MTX
Package Number
MS48A
MS48A
MTD48
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Devices also available in Tape and Reel. Specify by appending the suffix letter “x” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
T/R
n
A
0
–A
15
B
0
–B
15
Description
Output Enable Input
Transmit/Receive Input
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
© 2005 Fairchild Semiconductor Corporation
DS500052
www.fairchildsemi.com
Print form created on June 10, 2005 12:56 pm
74LCXR162245
Absolute Maximum Ratings
(Note 3)
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
Parameter
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature
Value
Conditions
Units
V
V
Output in 3-STATE
Output in HIGH or LOW State (Note 4)
V
I
GND
V
O
GND
V
O
!
V
CC
V
mA
mA
mA
mA
mA
0.5 to
7.0
0.5 to
7.0
0.5 to
7.0
0.5 to V
CC
0.5
50
50
50
r
50
r
100
r
100
65 to
150
q
C
Recommended Operating Conditions
(Note 5)
Symbol
V
CC
V
I
V
O
I
OH
/I
OL
Supply Voltage
Input Voltage
Output Voltage
Output Current
HIGH or LOW State
3-STATE
V
CC
V
CC
V
CC
T
A
Free-Air Operating Temperature
Input Edge Rate, V
IN
0.8V–2.0V, V
CC
3.0V
3.0V
3.6V
2.7V
3.0V
2.3V
2.7V
Parameter
Operating
Data Retention
Min
2.0
1.5
0
0
0
Max
3.6
3.6
5.5
V
CC
5.5
Units
V
V
V
r
12
r
8
r
4
40
0
85
10
mA
q
C
ns/V
'
t/
'
V
Note 3:
The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 4:
I
O
Absolute Maximum Rating must be observed.
Note 5:
Unused pins (Inputs or I/O's) must be held HIGH or LOW. They may not Float.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
Parameter
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Voltage
I
OH
I
OH
I
OH
I
OH
I
OH
I
OH
V
OL
LOW Level Output Voltage
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
I
I
I
OZ
Input Leakage Current
3-STATE I/O Leakage
Conditions
V
CC
(V)
2.3
2.7
2.7
3.6
2.3
2.7
2.7
3.6
T
A
Min
1.7
2.0
0.7
0.8
V
CC
0.2
1.8
2.2
2.4
2.0
2.0
0.2
0.6
0.4
0.55
0.6
0.8
V
V
40
q
C to
85
q
C
Max
Units
V
V
100
P
A
4 mA
4 mA
6 mA
8 mA
12 mA
100
P
A
4 mA
4 mA
6 mA
8 mA
12 mA
2.3
3.6
2.3
2.7
3.0
2.7
3.0
2.3
3.6
2.3
2.7
3.0
2.7
3.0
2.3
3.6
2.3
3.6
0
d
V
I
d
5.5V
0
d
V
O
d
5.5V
V
I
V
IH
or V
IL
r
5.0
r
5.0
P
A
P
A
3
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74LCXR162245
DC Electrical Characteristics
Symbol
I
OFF
I
CC
Parameter
Power-Off Leakage Current
Quiescent Supply Current
Increase in I
CC
per Input
(Continued)
V
CC
(V)
0
2.3
3.6
2.3
3.6
2.3
3.6
T
A
Min
Conditions
V
I
or V
O
V
I
V
IH
5.5V
40
q
C to
85
q
C
Max
10
20
Units
P
A
P
A
P
A
V
CC
or GND
V
CC
0.6V
3.6V
d
V
I
, V
O
d
5.5V (Note 6)
r
20
500
'
I
CC
Note 6:
Outputs disabled or 3-STATE only.
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
C
L
Min
t
PHL
t
PLH
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSHL
t
OSLH
Output to Output Skew (Note 7)
Output Disable Time
Propagation Delay
A
n
to B
n
or B
n
to A
n
Output Enable Time
1.5
1.5
1.5
1.5
1.5
1.5
3.3V
r
0.3V
50 pF
Max
5.3
5.3
7.3
7.3
6.4
6.4
1.0
1.0
40
q
C to
85
q
C, R
L
V
CC
C
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
2.7V
50 pF
Max
6.0
6.0
8.0
8.0
6.9
6.9
500
:
V
CC
C
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
2.5V
r
0.2
30 pF
Max
6.4
6.4
9.5
9.5
7.7
7.7
ns
ns
ns
ns
Units
Note 7:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Dynamic Peak V
OL
Quiet Output Dynamic Valley V
OL
C
L
C
L
C
L
C
L
50 pF, V
IH
30 pF, V
IH
50 pF, V
IH
30 pF, V
IH
Conditions
3.3V, V
IL
2.5V, V
IL
3.3V, V
IL
2.5V, V
IL
0V
0V
0V
0V
V
CC
(V)
3.3
2.5
3.3
2.5
T
A
25
q
C
Units
Typical
0.35
0.25
V
V
0.35
0.25
Capacitance
Symbol
C
IN
C
I/O
C
PD
Input Capacitance
Input/Output Capacitance
Power Dissipation Capacitance
Parameter
V
CC
V
CC
V
CC
Open, V
I
3.3V, V
I
3.3V, V
I
Conditions
0V or V
CC
0V or V
CC
0V or V
CC
, f
10 MHz
Typical
7
8
20
Units
pF
pF
pF
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4
74LCXR162245
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Test
t
PLH
, t
PHL
t
PZL
, t
PLZ
t
PZH
,t
PHZ
Switch
Open
6V at V
CC
3.3
r
0.3V
V
CC
x 2 at V
CC
2.5
r
0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and t
rec
Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
R
= t
F
= 3ns)
Symbol
V
mi
V
mo
V
x
V
y
V
CC
3.3V
r
0.3V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
2.7V
1.5V
1.5V
V
OL
0.3V
V
OH
0.3V
t
rise
and t
fall
2.5V
r
0.2V
V
CC
/2
V
CC
/2
V
OL
0.15V
V
OH
0.15V
5
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