• Capable of withstanding greater than 2001V electro-
static discharge
• V
IH
of 2.2V
provided by an active LOW Chip Enable (CE), and active LOW
Output Enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
0
through I/O
7
) is written into the
memory location specified on the address pins (A
0
through
A
10
).
Reading the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while Write Enable (WE)
remains HIGH. Under these conditions, the contents of the
memory location specified on the address pins will appear on
the eight I/O pins.
The I/O pins remain in high-impedance state when Chip En-
able (CE) or Output Enable (OE) is HIGH or Write Enable (WE)
is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
Logic Block Diagram
Pin Configurations
DIP/SOJ/SOIC
Top View
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
24
23
2
22
3
4
21
5
20
6
19
7C128A
18
7
17
8
9
16
10
15
11
14
12
13
V
CC
A
8
A
9
WE
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
C128A–2
INPUT BUFFER
I/O
0
I/O
1
ROW DECODER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
CE
WE
OE
I/O
2
SENSE AMPS
128 x 16 x 8
ARRAY
I/O
3
I/O
4
I/O
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
LCC
Top View
A5
A6
A7
VCC
A8
3 2 1 24 23
4
22
5
21
6
20
7 7C128A 19
8
18
9
17
10
16
11 12 13 14 15
I/O 2
GND
I/O 3
I/O 4
I/O 5
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
9
WE
OE
A
10
CE
I/O
7
I/O
6
C128A–3
A
3
A
2
A
1
A
0
C128A–1
Selection Guide
Maximum Access Time (ns)
Maximum Operating
Commercial
Current (mA)
Military
Maximum Standby
Commercial
Current (mA)
Military
7C128A-15
15
120
-
40
-
7C128A-20
20
120
125
20
20
7C128A-25
25
120
125
20
20
7C128A-35
35
120
125
20
20
7C128A-45
45
120
125
20
20
Cypress Semiconductor Corporation
Document #: 38-05028 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
[+] Feedback
CY7C128A
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Military
[1]
Ambient
Temperature
0
°
C to +70
°
C
–55
°
C to +125
°
C
V
CC
5V
±
10%
5V
±
10%
Electrical Characteristics
Over the Operating Range
[2]
7C128A-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[3]
Input Load
Current
Output Leakage
Current
Output Short
CircuitCurrent
[4]
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current
Automatic CE
Power-Down
Current
GND < V
I
< V
CC
GND < V
I
< V
CC
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.
I
OUT
= 0 mA
Max. V
CC
,
CE > V
IH,
Min. Duty Cycle
= 100%
Max. V
CC
,
CE
1
>V
CC
–0.3V,
V
IN
> V
CC
–0.3V
or V
IN
< 0.3V
Com’l
Mil
Com’l
Mil
Com’l
Mil
Test Conditions
V
CC
= Min.,
I
OH =
–4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–10
–10
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
120
-
40
-
40
-
2.2
–0.5
–10
–10
Max.
7C128A-20
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
120
125
40
40
20
20
2.2
–0.5
–10
–10
Max.
7C128A-25
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
120
125
20
40
20
20
2.2
–0.5
–10
–10
Max.
7C128A-35,45
Min.
2.4
0.4
V
CC
0.8
+10
+10
–300
120
125
20
20
20
20
mA
mA
Max.
Unit
V
V
V
V
µA
µA
mA
mA
I
SB2
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. V
IL
(min.) = –3.0V for pulse durations less than 30 ns.
4. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05028 Rev. **
Page 2 of 10
[+] Feedback
CY7C128A
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
R2
255
Ω
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
R1 481
Ω
ALL INPUT PULSES
3.0V
GND
10%
90%
90%
10%
≤
5 ns
≤
5 ns
(a)
(b)
C128A–4
C128A–5
THÉVENIN EQUIVALENT
167
Ω
1.73V
OUTPUT
Switching Characteristics
Over the Operating Range
[2, 6]
7C128A-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[7]
CE LOW to Low Z
[8]
CE HIGH to High Z
[7, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
[9]
7C128A-20
Min.
20
Max.
7C128A-25
Min.
25
Max.
7C128A-35
Min.
35
Max.
7C128A-45
Min.
45
Max.
Unit
ns
45
5
45
20
3
15
5
15
0
25
40
30
30
0
0
20
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
5
ns
ns
Description
Min.
15
Max.
15
5
15
10
3
8
5
8
0
15
15
12
12
0
0
12
10
0
7
5
5
20
15
15
0
0
15
10
0
0
5
3
5
20
5
20
10
3
8
5
8
0
20
20
20
20
0
0
15
10
0
7
5
25
5
25
12
3
10
5
10
0
20
25
25
25
0
0
20
15
0
7
5
35
35
15
12
15
20
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[7]
WE HIGH to Low Z
10
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady state voltage.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05028 Rev. **
Page 3 of 10
[+] Feedback
CY7C128A
Switching Waveforms
Read Cycle No. 1
[10, 11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C128A–6
Read Cycle No. 2
[10, 12]
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
PD
I
CC
50%
I
SB
C128A–7
t
RC
t
HZOE
t
HZCE
DATA VALID
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[9, ]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
DATA UNDEFINED
C128A–8
t
AW
t
PWE
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
Notes:
10. WE is HIGH for read cycle.
11. Device is continuously selected. OE, CE = V
IL
.
12. Address valid prior to or coincident with CE transition LOW.
13. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write.
Document #: 38-05028 Rev. **
Page 4 of 10
[+] Feedback
CY7C128A
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
[9, 13, 14]
t
WC
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
HIGH IMPEDANCE
DATA UNDEFINED
C128A–9
t
SCE
t
HA
t
HD
Notes:
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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