White Electronic Designs
PCMCIA SRAM MEMORY CARD — SEA SERIES
SRAM Memory Card 128KB Through 512KB
FEATURES
High Performance SRAM Memory Card
Single 5 Volt Supply
Fast Access Times: 150ns
x8 Interface (subset of PCMCIA standard)
Low Power CMOS technology provides very low
power and reliable data retention characteristics
• Operating current 80mA maximum
• Standby current < 100μA typical
Rechargeable Lithium battery with recharge
circuitry
• Eliminates the need for replaceable batteries
• Standby current during recharge typically < 2mA
• Battery backup time
18 months - typical typical based on 512kB (lower
densities will have greater storage times)
Unlimited write cycles, no endurance issues
2KB EEPROM attribute memory containing CIS
(optional)
Optional Hardware Write Protect Switch
PC Card Standard Type I Form Factor
SEA01-SEA04
GENERAL DESCRIPTION
The WEDC SEA SRAM Series memory cards offer a high
performance nonvolatile storage solution for code and
data storage, disk caching, and write intensive mobile and
embedded applications.
Packaged in PCMCIA type I housing the WEDC SRAM
SEA series is based on 1 or 4Mbit SRAM memories,
providing densities from 128 Kbytes to 512 Kbytes.
The SEA series of SRAM memory cards requires a 5V
power supply and operates at speeds to 150ns. The cards
are based on advanced CMOS technology providing very
low power and reliable data retention characteristics.
WEDC’s SRAM cards contain a rechargeable lithium
battery and recharge circuitry, eliminating the need for
replaceable batteries found in many SRAM cards.
WEDC’s standard cards are shipped with WEDC’s SRAM
Logo. Cards are also available with blank housings
(no Logo). The blank housings are available in both a
recessed (for label) and
fl
at housing. Please contact
WEDC sales representative for further information on
Custom artwork.
February 2007
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
BLOCK DIAGRAM
SEA01-SEA04
[A0..A18]
ADDREsS BUS
512KB SRAM Card Shown
+ + + + +
CE1#
CE2#
WE#
OE#
REG#
A0
decoder
and
control
logic
CS#
CS#-A
RD#
WR#
CTRL
RD#
WR#
[A1..A11]
ATTRIBUTE
MEMORY
optional
SRAM
512K x 8
S1
WP
Write Prot
Switch
VS1
VS2
GND
NC
NC
Vcc
CS#-A
RD#
WR#
CTRL
I/O BUFFER
[DO..D7]
[DO..D7]
Notes:
Vcc
1. pull down resistor (min 100k)
+
+
BVD1
BVD2
Power Management
and
Battery Control
2. pull up resistor (min 10k)
to internal
power
supply
Lithium Bat.
February 2007
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PINOUT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Signal name
GND
DQ3
DQ4
DQ5
DQ6
DQ7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
NC
Vcc
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
WP
GND
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
Function
Ground
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
Card enable 1
Address bit 10
Output enable
Address bit 11
Address bit 9
Address bit 8
Address bit 13
Address bit 14
Write Enable
Supply Voltage
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
O
Address bit 16
Address bit 15
Address bit 12
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit 1
Address bit 0
Data bit 0
Data bit 1
Data bit 2
Write Potect
Ground
128KB(2)
Active
Pin
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Signal name
GND
CD1#
NC
NC
NC
NC
NC
NC
VS1
NC
NC
A17
A18
NC
NC
NC
Vcc
NC
NC
NC
NC
NC
VS2
NC
Wait#
NC
REG#
BVD2
BVD1
DQ8
DQ9
DQ10
CD2#
GND
I/O
O
I/O
I/O
I/O
I/O
I
I
O
SEA01-SEA04
LOW
LOW
Function
Ground
Card Detect 1
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Card Enable 2
Voltage Sense 1
Active
LOW
LOW
N.C.
LOW
I
I
I
I
I
Address bit 17
Address bit 18
Address bit 19
Address bit 20
Address bit 21
Supply Voltage
Address bit 22
Address bit 23
Address bit 24
Address bit 25
Voltage Sense 2
Extended Bus Cycle
Attrib Mem Select
Bat. Volt. Detect 2
Bat. Volt. Detect 1
Data bit 8
Data bit 9
Data bit 10
Card Detect 2
Ground
512KB(2)
.
O
O
I
O
O
I/O
I/O
O
O
N.C.
Low
Low
(3)
HIGH
LOW
Notes:
1. CD1# and CD2# are grounded internal to PC Card.
2. Shows density for which specified address bit is MSB. Higher order address bits are
no connects (i.e., 512kB A18 is MSB, A19 - A21 are NC).
3. BVD1 is an open drain output with a 10K ohm internal pull-up resistor.
February 2007
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PACKAGE DIMENSIONS
SEA01-SEA04
Type I
Interconnect area
1.6mm
± 0.05
(0.063”)
10.0mm MIN
(0.400”)
3.0mm MIN
1.0mm ± 0.05
(0.039”)
Substrate area
54.0mm ± 0.10
(2.126”)
1.0mm ± 0.05
(0.039”)
85.6mm ± 0.20
(3.370”)
10.0mm MIN
(0.400”)
3.3mm ± T1 (0.130”)
T1=0.10mm interconnect area
T1=0.20mm substrate area
February 2007
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
CARD SIGNAL DESCRIPTION
Symbol
A0 - A25
Type
INPUT
Name and Function
SEA01-SEA04
ADDRESS INPUTS:
A0 through A25 enable direct addressing of up to 64MB of memory on the card. Signal A0 is not
used in word access mode. A25 is the most significant bit. (address pins used are based on card density,see pinout
for highest used address pin)
DATA INPUT/OUTPUT:
DQ0 THROUGH DQ15 constitute the bi-directional databus. DQ0 - DQ7 constitute the lower
(even) byte and DQ8 - DQ15 the upper (odd) byte. Upper byte is Not Connected on this card.
CARD ENABLE 1 AND 2:
CE1# enables even byte accesses, CE2# control signal in PCMCIA standard, to access
high byte, - not used on this card
OUTPUT ENABLE:
Active low signal enabling read data from the memory card.
WRITE ENABLE:
Active low signal gating write data to the memory card.
READY/BUSY OUTPUT:
Not used for SRAM cards
CARD DETECT 1 and 2:
Provide card insertion detection. These signals are connected to ground internally on the
memory card. The host socket interface circuitry shall supply 10K-ohm or larger pull-up resistors on these signal pins.
WRITE PROTECT:
Follows hardware Write Protect Switch. When Switch is placed in on position, signal is pulled high
(10K ohm). When switch is off signal is pulled low.
PROGRAM/ERASE POWER SUPPLY:
Not used for SRAM cards.
CARD POW ER SUPPLY:
5.0V for all internal circuitry.
GROUND:
for all internal circuitry.
DQ0 – DQ7
DQ8 – DQ15
CE1#, CE2#
OE#
WE#
RDY/BSY #
CD1#, CD2#
WP
VPP1, VPP2
V
CC
GND
REG #
RST
WAIT #
BVD1, BVD2
INPUT/OUTPUT
INPUT
INPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
INPUT
INPUT
OUTPUT
OUTPUT
ATTRIBUTE MEMORY SELECT:
only used with cards built with optional attribute memory.
RESET:
Not used for SRAM cards
WAIT:
This signal is pulled high internally for compatibility. No wait states are generated.
BATTERY VOLTAGE DETECT:
Provides status of Battery voltage.
BVD2 = BVD1 = V
OH
(battery voltage is guaranteed to retain data)
BVD2 = V
OL
, BVD1 = V
OH
(data is valid, battery recharge required)
BVD2 = BVD1 = V
OL
(data may no longer be valid, battery requires extended recharge)
VOLTAGE SENSE: Notifies the host socket of the card’s V
CC
requirements. VS1 and VS2 are open to indicate a 5V,
16 bit card has been inserted.
RESERVED FOR FUTURE USE
NO INTERNAL CONNECTION TO CARD: pin may be driven or left
fl
oating
VS1, VS2
RFU
N.C.
OUTPUT
FUNCTIONAL TRUTH TABLE
READ function
Function Mode
Standby Mode
Byte Access (8 bits)
WRITE function
Standby Mode
Byte Access (8 bits)
February 2007
Rev. 4
CE2# CE1# OE#
X
H
X
X
L
L
X
X
H
L
X
H
WE#
X
H
X
L
REG#
X
H
X
H
Common Memory
D15-D8
D7-D0
High-Z
High-Z
High-Z
Data Out
X
X
5
REG#
X
L
X
L
Attribute Memory
D15-D8
D7-D0
High-Z
High-Z
High-Z
Data Out
X
X
X
Data In
X
Data In
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
FPGA/CPLD
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