CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
36-Mbit (1 M × 36/2 M × 18/512 K × 72)
Pipelined Sync SRAM
36-Mbit (1 M × 36/2 M × 18/512 K × 72) Pipelined Sync SRAM
Features
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Functional Description
[1]
The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM
integrates 1 M × 36/2 M × 18 and 512 K × 72 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
X
and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and the ZZ
pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see pin descriptions and truth table for further
details). Write cycles can be one to two or four bytes wide as
controlled by the byte write control inputs. GW when active LOW
causes all bytes to be written.
The
CY7C1440AV33/CY7C1442AV33/CY7C1446AV33
operates from a +3.3 V core power supply while all outputs may
operate with either a +2.5 or +3.3 V supply. All inputs and outputs
are JEDEC-standard JESD8-5-compatible.
Supports bus operation up to 250 MHz
Available speed grades are 250, 200 and 167 MHz
Registered inputs and outputs for pipelined operation
3.3 V core power supply
2.5 V/3.3 V I/O power supply
Fast clock-to-output times
❐
2.6 ns (for 250-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Single cycle chip deselect
CY7C1440AV33, CY7C1442AV33 available in Pb-free 100-pin
TQFP package, Pb-free and non Pb-free 165-ball FBGA
package. CY7C1446AV33 available in Pb-free and non Pb-free
209-ball FBGA package
Also available in Pb-free packages
IEEE 1149.1 JTAG-compatible boundary scan
“ZZ” sleep mode option
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Note
1. For best-practices recommendations, please refer to the Cypress application note
System Design Guidelines
on
www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05383 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 12, 2010
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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Contents
Selection Guide ................................................................ 5
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 7
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................... 9
Burst Sequences ......................................................... 9
Sleep Mode ................................................................. 9
Interleaved Burst Address Table
(MODE = Floating or V
DD
) .............................................. 10
Linear Burst Address Table (MODE = GND) ................ 10
ZZ Mode Electrical Characteristics ............................... 10
Truth Table ..................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
TAP Controller State Diagram ....................................... 13
Test Access Port (TAP) ............................................. 13
TAP Controller Block Diagram ...................................... 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Timing ..................................................................... 15
TAP AC Switching Characteristics ............................... 16
3.3 V TAP AC Test Conditions ....................................... 16
3.3 V TAP AC Output Load Equivalent ......................... 16
2.5 V TAP AC Test Conditions ....................................... 16
2.5 V TAP AC Output Load Equivalent ......................... 16
TAP DC Electrical Characteristics and
Operating Conditions ..................................................... 17
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Identification Codes ....................................................... 17
165-ball FBGA Boundary Scan Order .......................... 18
209-ball FBGA Boundary Scan Order .......................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
Capacitance .................................................................... 21
Thermal Resistance ........................................................ 21
AC Test Loads and Waveforms ..................................... 21
Switching Characteristics .............................................. 22
Switching Waveforms .................................................... 23
Read Cycle Timing .................................................... 23
Write Cycle Timing .................................................... 24
Read/Write Cycle Timing ........................................... 25
ZZ Mode Timing ........................................................ 26
Ordering Information ...................................................... 27
Ordering Code Definitions ......................................... 27
Package Diagrams .......................................................... 28
Acronyms ........................................................................ 31
Document Conventions ................................................. 31
Units of Measure ....................................................... 31
Document History Page ................................................. 32
Sales, Solutions, and Legal Information ...................... 34
Worldwide Sales and Design Support ....................... 34
Products .................................................................... 34
PSoC Solutions ......................................................... 34
Document Number: 38-05383 Rev. *H
Page 4 of 34
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