12 Lane 3-Port PCI Express® Switch
89PES12N3
Product Brief
The PES12N3, a 12 lane 3-port PCI Express® switch, is a member
of IDT’s PRECISE™ family of PCI Express switching solutions. The
PES12N3 is a peripheral chip that performs PCI Express Base switching
with a feature set optimized for high performance applications such as
servers and storage. It provides connectivity and switching functions
between a PCI Express upstream port and two downstream ports or
peer-to-peer switching between downstream ports.
Device Overview
Features
◆
High Performance PCI Express Switch
– Three x4 ports with 12 PCI lanes total
– Delivers 6 GBps (48 Gbps) aggregate switching capacity
– Low latency cut-through switch architecture
– Supports 128 to 256 byte maximum payload size
– Supports one virtual channel
– PCI Express Base specification Revision 1.0a compliant
◆
Flexible Architecture with Numerous Configuration Options
– Port arbitration schemes utilizing round robin or weighted
round robin algorithms
– Supports automatic per port link with negotiation (x4, x2, or x1)
– Supports static lane reversal on all ports
– Supports polarity inversion
– Supports locked transactions, allowing use with legacy soft-
ware
– Ability to load device configuration from serial EEPROM
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates 12 2.5 Gbps embedded SerDes, 8B/10B encoder/
decoder (no separate transceivers needed)
◆
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC passed through
– Supports PCI Express Native Hot-Plug
• Compatible with Hot-Plug I/O expanders used on PC moth-
erboards
– Supports Hot-Swap
◆
Power Management
– Supports PCI Express Power Management Interface Specifi-
cation, Revision 1.1 (PCI-PM)
– Unused SerDes are disabled
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
◆
Testability and Debug Features
– Supports IEEE 1149.6 JTAG
– Built in SerDes Pseudo-Random Bit Stream (PRBS) generator
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
◆
Block Diagram
3-Port Switch Core
Frame Buffer
Route Table
Port
Arbitration
Scheduler
Scheduler
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Transaction Layer
Data Link Layer
Multiplexer/Demultiplexer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
Phy
Logical
Layer
SerDes SerDes SerDes SerDes
SerDes SerDes SerDes
SerDes
SerDes SerDes SerDes SerDes
12 PCI Express Lanes
One x4 Upstream Port and Two x4 Downstream Ports
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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©
2006 Integrated Device Technology, Inc.
February 15, 2006
DSC 6801
IDT
◆
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Two SMBus Interfaces
8 General Purpose Input/Output pins
Packaged in 19x19mm 324 ball BGA with 1mm ball spacing
Product Description
Utilizing standard PCI Express interconnect the PES12N3 provides
the most efficient high-performance I/O connectivity device for applica-
tions requiring high throughput, low latency and simple board layout. It
provides 6 GBps (48 Gbps) of aggregated, full-duplex switching capacity
through 12 integrated serial lanes. Each lane provides 2.5 Gbps of
bandwidth in both directions and is fully compliant with PCI Express
Base specification 1.0a.
The PES12N3 is based on a flexible and efficient layered architec-
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 1.0a. The PES12N3 can operate either as a store and forward
or cut-through switch depending on the packet size and is designed to
switch memory and I/O transactions. It supports eight Traffic Classes
(TCs) and one Virtual Channel (VC) with sophisticated resource
management. This includes system selectable algorithms such as round
robin, weighted round-robin, and strict priority schemes guaranteeing
bandwidth allocation and/or latency for critical traffic classes.
Processor
North
Bridge
Memory
Memory
Memory
Memory
PES12N3
PES12N3
PES12N3
PCI Express
Slots
I/O
1GbE
I/O
1GbE
I/O
SATA
I/O
SATA
Figure 1 I/O Expansion Application
August 16, 2004August 16, 200
CORPORATE HEADQUARTERS
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San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
for Tech Support:
email: ssdhelp@idt.com
phone: 408-284-8208
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