by holding critical DSP code and parameters in the cache for immediate
availability. The microprocessor also implements an on-chip MMU with a
TLB, making the it fully compliant with the requirements of real time
operating systems.
Memory and IO Controller
The RC32351 incorporates a flexible memory and peripheral device
controller providing support for SDRAM, Flash ROM, SRAM, dual-port
memory, and other I/O devices. It can interface directly to 8-bit boot
ROM for a very low cost system implementation. It enables access to
high bandwidth external memory (200 MB/sec peak) at very low system
costs. It also offers various trade-offs in cost / performance for the main
memory architecture. The timers implemented on the RC32351 satisfy
the requirements of most RTOS.
DMA Controller
The DMA controller off-loads the CPU core from moving data among
the on-chip interfaces, external peripherals, and memory. The DMA
controller supports scatter / gather DMA with no alignment restrictions,
appropriate for communications and graphics systems.
Ethernet Interface
The RC32351 contains an on-chip Ethernet MAC capable of 10 and
100 Mbps line interface with an MII interface. It supports up to 4 MAC
addresses. In a SOHO router, the high performance RC32300 CPU core
routes the data between the Ethernet and the ATM interface. In other
applications, such as high speed modems, the Ethernet interface can be
used to connect to the PC.
USB Device Interface
The RC32351 includes the industry standard USB device interface to
enable consumer appliances to directly connect to the PC.
ATM SAR
The RC32351 includes a configurable ATM SAR that supports a
UTOPIA level 1 or a UTOPIA level 2 interface. The ATM SAR is imple-
mented as a hybrid between software and hardware. A hardware block
provides the necessary low level blocks (like CRC generation and
checking and cell buffering) while the software is used for higher level
SARing functions. In xDSL modem applications, the UTOPIA port inter-
faces directly to an xDSL chip set. In SOHO routers or in a line card for a
Layer 3 switch, it provides access to an ATM network.
Enhanced JTAG Interface for ICE
For low-cost In-Circuit Emulation (ICE), the RC32300 CPU core
includes an Enhanced JTAG (EJTAG) interface. This interface consists
of two operation modes: Run-Time Mode and Real-Time Mode.
The Run-Time Mode provides a standard JTAG interface for on-chip
debugging, and the Real-Time Mode provides additional status pins—
PCST[2:0]—which are used in conjunction with the JTAG pins for real-
time trace information at the processor internal clock or any division of
the pipeline clock.
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May 25, 2004
IDT 79RC32351
Thermal Considerations
The RC32351 consumes less than 1.5 W peak power and is guaran-
teed in an ambient temperature range of 0° to
+70°
C (commercial).
Revision History
January 7, 2002:
Initial publication.
May 20, 2002:
Added values (in place of TBD) to Table 18, Power
Consumption.
September 19, 2002:
Added COLDRSTN Trise1 parameter to Table
5, Reset and System AC Timing Characteristics.
December 6, 2002:
In Features section, changed UART speed from
115 Kb/s to 1.5 Mb/s.
December 17, 2002:
Added V
OH
parameter to Table 16, DC Elec-
trical Characteristics.
May 25, 2004:
In Table 7, signals MIIRXCLK and MIITXCLK, the Min
and Max values for
10
Mbps Thigh1/Tlow1 were changed to 140 and
260 respectively and the Min and Max values for 100 Mbps Thigh1/
Tlow1 were changed to 14.0 and 26.0 respectively.
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May 25, 2004
IDT 79RC32351
Pin Description Table
The following table lists the functions of the pins provided on the RC32351. Some of the functions listed may be multiplexed onto the same pin.
To define the active polarity of a signal, a suffix will be used. Signals ending with an “N” should be interpreted as being active, or asserted, when at
a logic zero (low) level. All other signals (including clocks, buses and select lines) will be interpreted as being active, or asserted when at a logic one
(high) level.
Note:
The input pads of the RC32351 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate levels.
This is especially critical for unused control signal inputs (such as BRN) which, if left floating, could adversely affect the RC32351’s opera-
tion. Also, any input pin left floating can cause a slight increase in power consumption.
Name
System
CLKP
COLDRSTN
RSTN
I
I
I/O
Input
STI
1
System Clock input.
This is the system master clock input. The RISCore 32300 pipeline frequency is a multiple (x2, x3, or
x4) of this clock frequency. All other logic runs at this frequency or less.
Cold Reset.
The assertion of this signal low initiates a cold reset. This causes the RC32351 state to be initialized, boot
configuration to be loaded, and the internal processor PLL to lock onto the system clock (CLKP).
Type I/O Type
Description
Low Drive
Reset.
This bidirectional signal is either driven low or tri-stated, an external pull-up is required to supply the high state. The
with STI RC32351 drives RSTN low during a reset (to inform the external system that a reset is taking place) and then tri-states it.
The external system can drive RSTN low to initiate a warm reset, and then should tri-state it.
High Drive
System clock output.
This is a buffered and delayed version of the system clock input (CLKP). All SDRAM transactions
are synchronous to this clock. This pin should be externally connected to the SDRAMs and to the RC32351 SDCLKINP pin
(SDRAM clock input).
[21:0] High
Memory Address Bus.
26-bit address bus for memory and peripheral accesses. MADDR[20:17] are used for the
SODIMM data mask enables if SODIMM mode is selected.
Drive
[25:22] Low MADDR[22] Primary function: General Purpose I/O, GPIOP[27].
Drive with MADDR[23] Primary function: General Purpose I/O, GPIOP[28].
MADDR[24] Primary function: General Purpose I/O, GPIOP[29].
STI
MADDR[25] Primary function: General Purpose I/O, GPIOP[30].
SYSCLKP
O
Memory and Peripheral Bus
MADDR[25:0]
O
MDATA[31:0]
BDIRN
BOEN[1:0]
I/O
O
O
High Drive
Memory Data Bus.
32-bit data bus for memory and peripheral accesses.
High Drive
External Buffer Direction.
External transceiver direction control for the memory and peripheral data bus, MDATA[31:0]. It
is asserted low during any read transaction, and remains high during write transactions.
High Drive
External Buffer Output Enable.
These signals provide two output enable controls for external data bus transceivers on
the memory and peripheral data bus, MDATA. BOEN[0] is asserted low during external device read transactions. BOEN[1]
is asserted low during SDRAM read transactions.
STI
External Bus Request.
This signal is asserted low by an external master device to request ownership of the memory and
peripheral bus.
BRN
BGN
WAITACKN
I
O
I
Low Drive
External Bus Grant.
This signal is asserted low by RC32351 to indicate that RC32351 has relinquished ownership of the
local memory and peripheral bus to an external master.
STI
Wait or Transfer Acknowledge.
When configured as wait, this signal is asserted low during a memory and peripheral
device bus transaction to extend the bus cycle. When configured as transfer acknowledge, this signal is asserted low dur-
ing a memory and peripheral device bus transaction to signal the completion of the transaction.
CSN[5:0]
O
Device Chip Select.
These signals are used to select an external device on the memory and peripheral bus during device
[3:0]
High Drive transactions. Each bit is asserted low during an access to the selected external device.
CSN[4] Primary function: General purpose I/O, GPIOP[16].
CSN[5] Primary function: General purpose I/O, GPIOP[17].
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