Enhanced N channel FET with no inherent diode to Vcc
Bidirectional signal flow
Flow-through pinout
Zero propagation delay, zero ground bounce
16 banks of 2:1 Mux/Demux
Port select synchronous to the clock
Clock enable and asynchronous enable
Undershoot clamp diodes on all switch and control inputs
Asynchronous SEL option
Break-before-make feature
Bus-hold eliminates floating bus lines and reduces static power
consumption
• Available in 80-pin Millipaq package
•
•
•
•
•
•
•
•
•
•
•
IDTQS34XS257
DESCRIPTION:
The QS34XS257 is a high-speed CMOS quad 32:16 multiplexer/
demultiplexer. It is organized as four independent quad 2:1 mux/demux
blocks. Port selection and connection, controlled by SEL signals, can be
either asynchronous or synchronous. In the synchronous mode, the A or
B port to Y port connection is updated on the rising edge of the input clock
CLK. Once the port-to-port connection is made, data flow can be bi-
directional with a typical 250ps propagation delay through the switch. Clock
Enable, overriding Asynchronous Enable, and Asynchronous Select con-
trols provide additional design flexibility.
Synchronous controls ease timing constraints in many high speed data
mux/demux applications, such as bank interleaving. The QS34XS257 is
available in the space-saving, 80-pin dual-in-line MillipaQ package.
The QS34XS257 is characterized for operation at -40°C to +85°C.
APPLICATIONS:
• Memory interleaving
FUNCTIONAL BLOCK DIAGRAM
SELn
CLKn
CLKENn
OEn
SYNCn
CONTROL
LOGIC
An
0
Yn
0
Bn
0
An
1
Yn
1
Bn
1
An
2
Yn
2
Bn
2
An
3
Yn
3
Bn
3
NOTE:
1. One of four blocks shown.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2006 Integrated Device Technology, Inc.
JUNE 2006
DSC-5578/3
IDTQS34XS257
HIGH-SPEED CMOS SYNCHROSWITCH 32:16 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
NC
A
00
A
01
A
02
A
03
B
00
B
01
B
02
B
03
GND
NC
A
10
A
11
A
12
A
13
B
10
B
11
B
12
B
13
GND
NC
A
20
A
21
A
22
A
23
B
20
B
21
B
22
B
23
GND
NC
A
30
A
31
A
32
A
33
B
30
B
31
B
32
B
33
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Vcc
OE
0
SEL
0
Y
00
Y
01
Y
02
Y
03
CLKEN
0
CLK
0
SYNC
0
Vcc
OE
1
SEL
1
Y
10
Y
11
Y
12
Y
13
CLKEN
1
CLK
1
SYNC
1
Vcc
OE
2
SEL
2
Y
20
Y
21
Y
22
Y
23
CLKEN
2
CLK
2
SYNC
2
Vcc
OE
3
SEL
3
Y
30
Y
31
Y
32
Y
33
CLKEN
3
CLK
3
SYNC
3
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
V
TERM
(3)
V
AC
I
OUT
P
MAX
T
STG
Description
Supply Voltage to Ground
DC Switch Voltage Vs
DC Input Voltage V
IN
AC Input Voltage (pulse width
≤
20ns)
DC Output Current
Maximum Power Dissipation (T
A
= 85°C)
Storage Temperature
Max
–0.5 to +7
–0.5 to +7
–0.5 to +7
–3
120
1.16
–65 to +150
Unit
V
V
V
V
mA
W
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. All terminals except Vcc.
CAPACITANCE
(T
A
= +25°C, f = 1.0MH
Z
, V
IN
= 0V, V
OUT
= 0V)
Pins
Control Pins
Quickswitch Channels
(Switch OFF)
Demux
Mux
Typ.
4
5
7
Max.
(1)
5
7
9
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
An
0
- An
3
Bn
0
- Bn
3
Yn
0
- Yn
3
SELn
CLKn
CLKENn
OEn
SYNCn
I/O
I/O
I/O
I/O
I
I
I
I
I
Description
Demux Port A
Demux Port B
Mux Port Y
Select Input
Clock
Clock Enable
Output Enable
Synchronous Selection Enable
MILLIPAQ (Q3)
TOP VIEW
2
IDTQS34XS257
HIGH-SPEED CMOS SYNCHROSWITCH 32:16 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE
(1)
Control Inputs
SYNC
L
L
L
L
L
H
H
H
OEn
L
L
H
L
H
L
L
H
CLKn
↑
↑
↑
↑
↑
X
X
X
CLKENn
L
L
L
H
H
X
X
X
SELn
L
H
X
X
X
L
H
X
An
0
Bn
0
Yn
0
An
0
Bn
0
Yn
1
An
1
Bn
1
Port Status
Yn
2
An
2
Bn
2
Yn
3
An
3
Bn
3
Select Port A
Select Port B
Switch OFF
(2)
Hold Previous Mux connection
(3)
(Switch ON)
Switch OFF
(4)
An
3
Bn
3
Select Port A
Select Port B
Hold Previous Data (Switch OFF)
Function
No change in Mux connection
No change in Mux connection
No change in Mux connection
An
1
Bn
1
An
2
Bn
2
No change in Mux connection
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑
= LOW-to-HIGH Transition
2. Mux switches are turned off. The port connection can be changed by the SEL input.
3. The contents of the “Mux select register” are unchanged and the previous Mux connection is unchanged. The output (Mux port) data state will depend on the present
data state of the input (Demux port).
4. The contents of the “Mux select register” are unchanged.
CONTROL LOGIC
(1)
1
2:1
MU X
SE Ln
0
D
Q
0
2:1
MUX
1
CLKEN n
CLKn
SYN Cn
OEn
To Port A Switches
To Port B Switches
NOTE:
1. One of four blocks.
3
IDTQS34XS257
HIGH-SPEED CMOS SYNCHROSWITCH 32:16 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IN
R
ON
Parameter
Input HIGH Level
Input LOW Level
Input LeakageCurrent (Control Inputs)
Switch ON Resistance
(2,3)
Test Conditions
Guaranteed Logic HIGH for Control Pins
Guaranteed Logic LOW for Control Pins
0V
≤
V
IN
≤
V
CC
V
CC
= Min., V
IN
= 0V, I
ON
= 30mA
V
CC
= Min., V
IN
= 2.4V, I
ON
=15mA
Min.
2
—
—
—
—
Typ.
(1)
—
—
0.1
7
10
Max.
—
0.8
±1
9
13
Unit
V
V
µA
Ω
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. Max value of R
ON
is guaranteed but not production tested.
3. Measured by voltage drop between A/B and Y pin at indicated current through the switch.
TYPICAL ON RESISTANCE vs V
IN
AT V
CC
= 5V
16
14
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
R
ON
(ohms)
V
IN
(Volts)
4
IDTQS34XS257
HIGH-SPEED CMOS SYNCHROSWITCH 32:16 MUX/DEMUX
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
I
CCQ
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
Power Supply Current per Control Input HIGH
(2)
Dynamic Power Supply Current per MHz
(3)
Test Conditions
(1)
V
CC
= Max., V
CTRL
= GND or Vcc, f = 0
V
CC
= Max., V
IN
= 3.4V, f = 0
V
CC
= Max., A/B and Y pins open
Control Inputs Toggling at 50% Duty Cycle
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V, control inputs only). A/B and Y pins do not contribute to
ΔIcc.
3. This current applies to the control inputs only and represents the current required to switch internal capacitance at the specified frequency. The A/B and Y inputs generate no
significant AC or DC currents as they transition. This parameter is guaranteed but not production tested.
Max.
12
1.5
0.25
Unit
mA
mA
mA/MHz
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
T
A
= -40°C to +85°C, V
CC
= 5.0V ± 10%;
C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
Symbol
t
PLH
t
PHL
t
SEC
t
HEC
t
CSO
t
ASO
t
W
t
SCS
t
HCS
t
PZL
t
PZH
t
PLZ
t
PHZ
Data Propagation Delay
(2,3)
A/B to Y, Y to A/B
Clock Enable to Clock Setup Time
Clock Enable to Clock Hold Time
Clock to A, B Switch Turn-On Delay
Asynchronous Select to A, B Switch Turn-On Delay
Clock Pulse Width HIGH
Clock to SEL Setup Time
Clock to SEL Hold Time
Asynchronous Enable to Switch Turn-On Delay
Asynchronous Enable to Switch Turn-Off Delay
(2)
3
0
0.5
0.5
3
3
0
1.5
1.5
—
—
—
—
—
—
—
—
—
—
—
7
7
—
—
—
5.2
4.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
(1)
—
Typ.
0.25
Max.
—
Unit
ns
NOTES:
1.
Minimums are guaranteed but not production tested.
2. This parameter is guaranteed but not production tested.
3. The bus switch contributes no propagation delay other than the RC delay of the ON resistance of the switch and the load capacitance. The time constant for the switch alone
is of the order of 0.25ns for C
L
= 50pF. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagation delay to
the system. Propagation delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load
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