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IDT82V3010: 产品描述SPECIALTY TELECOM CIRCUIT, PDSO56; 产品类别热门应用无线/射频/通信; 文件大小345KB，共31页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

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IDT82V3010概述

SPECIALTY TELECOM CIRCUIT, PDSO56

专业电信电路, PDSO56

IDT82V3010规格参数

参数名称	属性值
功能数量	1
端子数量	56
最小工作温度	-40 Cel
最大工作温度	85 Cel
加工封装描述	GREEN, SSOP-56
each_compli	Yes
欧盟RoHS规范	Yes
状态	Active
通信类型	TELECOM CIRCUIT
jesd_30_code	R-PDSO-G56
jesd_609_code	e3
moisture_sensitivity_level	1
包装材料	PLASTIC/EPOXY
ckage_code	SSOP
包装形状	RECTANGULAR
包装尺寸	SMALL OUTLINE, SHRINK PITCH
eak_reflow_temperature__cel_	260
qualification_status	COMMERCIAL
seated_height_max	2.79 mm
额定供电电压	3.3 V
表面贴装	YES
温度等级	INDUSTRIAL
端子涂层	MATTE TIN
端子形式	GULL WING
端子间距	0.6350 mm
端子位置	DUAL
ime_peak_reflow_temperature_max__s_	30
length	18.42 mm
width	7.49 mm

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T1/E1/OC3 TELECOM CLOCK GENERATOR

WITH DUAL REFERENCE INPUTS

IDT82V3010

FEATURES

• Supports AT&T TR62411

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 timing

for E1 interface

• Selectable reference inputs: 8 kHz, 1.544 MHz, 2.048 MHz or

19.44 MHz

• Accepts two independent reference inputs which may have

same or different nominal frequencies applied to them

• Provides C1.5o,

C3o,

C2o,

C4o,

C6o, C8o,

C16o,

C19o and

C32o

output clock signals

• Provides 7 types of 8 kHz framing pulses:

F0o,

F8o,

F16o,

F19o,

F32o,

RSP and TSP

• Provides a C2/C1.5 output clock signal with the frequency

controlled by the selected reference input Fref0 or Fref1

•

Phase slope of 5 ns per 125 µs

Attenuates wander from 2.1 Hz

Fast lock mode

Provides Time Interval Error (TIE) correction

MTIE of 1 µs

JTAG boundary scan

Holdover status indication

Freerun status indication

Normal status indication

Lock status indication

Input reference quality indication

3.3 V operation with 5 V tolerant I/O

Package: 56-pin SSOP (Green option available)

FUNCTIONAL BLOCK DIAGRAM

TDO

TDI

OSCi

TCLR

RST

DDD

DDA

C2/C1.5

TCK

TMS

TRST

Fref0

Fref1

IN_sel

FLOCK

DPLL

JTAG

OSC

C32o

C19o

C19POS

C19NEG

TIE Control

Block

Virtual

Reference

Reference Input

Switch

C16o

C8o

C4o

C2o

C3o

C1.5o

C6o

F0o

F8o

F16o

F19o

F32o

RSP

TSP

LOCK

Frequency

Select Circuit 0

MON_out0

Reference Input

Monitor 0

Reference Input

Monitor 1

Feedback Signal

MON_out1

Invalid Input

Signal Detection

F0_sel0

F0_sel1

State Control Circuit

Frequency

Select Circuit 1

F1_sel0

F1_sel1

TIE_en MODE_sel1 MODE_sel0 Normal Holdover Freerun

IDT and IDT logo are trademarks of Integrated Device Technology, Inc.

2006

Integrated Device Technology, Inc.

June 19, 2006

DSC-6777/2

IDT82V3010

T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

TABLE OF CONTENTS

Pin Description...................................................................................................................................................................................................7

Functional Description ......................................................................................................................................................................................9

2.1 State Control Circuit ..................................................................................................................................................................................9

2.1.1 Normal Mode..............................................................................................................................................................................10

2.1.2 Fast Lock Mode..........................................................................................................................................................................10

2.1.3 Holdover Mode ...........................................................................................................................................................................10

2.1.4 Freerun Mode.............................................................................................................................................................................10

2.2 Frequency Select Circuit .........................................................................................................................................................................10

2.3 Reference Input Switch ...........................................................................................................................................................................10

2.4 Reference Input Monitor ..........................................................................................................................................................................11

2.5 Invalid Input Signal Detection ..................................................................................................................................................................11

2.6 TIE Control Block.....................................................................................................................................................................................11

2.7 DPLL Block..............................................................................................................................................................................................12

2.7.1 Phase Detector (PHD)................................................................................................................................................................12

2.7.2 Limiter.........................................................................................................................................................................................12

2.7.3 Loop Filter ..................................................................................................................................................................................13

2.7.4 Fraction Block.............................................................................................................................................................................13

2.7.5 Digital Control Oscillator (DCO)..................................................................................................................................................13

2.7.6 Lock Indicator .............................................................................................................................................................................13

2.7.7 Output Interface..........................................................................................................................................................................13

2.8 OSC.........................................................................................................................................................................................................14

2.8.1 Clock Oscillator ..........................................................................................................................................................................14

2.9 JTAG .......................................................................................................................................................................................................14

2.10 Reset, Lock and TIE Application .............................................................................................................................................................14

2.11 Power Supply Filtering Techniques .........................................................................................................................................................15

Measures of Performance ...............................................................................................................................................................................16

3.1 Intrinsic Jitter ...........................................................................................................................................................................................16

3.2 Jitter Tolerance........................................................................................................................................................................................16

3.3 Jitter Transfer ..........................................................................................................................................................................................16

3.4 Frequency Accuracy................................................................................................................................................................................16

3.5 Holdover Accuracy ..................................................................................................................................................................................16

3.6 Capture Range ........................................................................................................................................................................................16

3.7 Lock Range .............................................................................................................................................................................................16

3.8 Phase Slope ............................................................................................................................................................................................16

3.9 Time Interval Error (TIE)..........................................................................................................................................................................16

3.10 Maximum Time Interval Error (MTIE) ......................................................................................................................................................16

3.11 Phase Continuity .....................................................................................................................................................................................16

3.12 Phase Lock Time.....................................................................................................................................................................................17

Absolute Maximum Ratings ............................................................................................................................................................................18

Recommended DC Operating Conditions .....................................................................................................................................................18

DC Electrical Characteristics ..........................................................................................................................................................................18

6.1 Single End Input/Output Port...................................................................................................................................................................18

6.2 Differential Output Port (LVDS) ...............................................................................................................................................................19

AC Electrical Characteristics ..........................................................................................................................................................................20

7.1 Performance ............................................................................................................................................................................................20

7.2 Intrinsic Jitter Unfiltered ...........................................................................................................................................................................20

7.3 C1.5o (1.544 MHz) Intrinsic Jitter Filtered ...............................................................................................................................................21

7.4 C2o (2.048 MHz) Intrinsic Jitter Filtered ..................................................................................................................................................21

7.5 C19o (19.44 MHz) Intrinsic Jitter Filtered ................................................................................................................................................21

7.6 8 kHz Input to 8 kHz Output Jitter Transfer .............................................................................................................................................21

7.7 1.544 MHz Input to 1.544 MHz Output Jitter Transfer.............................................................................................................................22

7.8 2.048 MHz Input to 2.048 MHz Output Jitter Transfer.............................................................................................................................22

June 19, 2006

Table Of Contents

IDT82V3010

T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs

LIST OF FIGURES

Figure - 1

Figure - 2

Figure - 3

Figure - 4

Figure - 5

Figure - 6

Figure - 7

Figure - 8

Figure - 9

Figure - 10

Figure - 11

Figure - 12

Figure - 13

Figure - 14

Figure - 15

IDT82V3010 SSOP56 Package Pin Assignment ................................................................................................................................ 2

State Control Circuit ............................................................................................................................................................................ 9

State Control Diagram......................................................................................................................................................................... 9

TIE Control Block Diagram................................................................................................................................................................ 11

Reference Switch with TIE Control Block Enabled............................................................................................................................ 12

Reference Switch with TIE Control Block Disabled........................................................................................................................... 12

DPLL Block Diagram ......................................................................................................................................................................... 13

Clock Oscillator Circuit ...................................................................................................................................................................... 14

Power-Up Reset Circuit..................................................................................................................................................................... 14

IDT82V3010 Power Decoupling Scheme.......................................................................................................................................... 15

Timing Parameter Measurement Voltage Levels .............................................................................................................................. 26

Input to Output Timing (Normal Mode).............................................................................................................................................. 28

Output Timing 1................................................................................................................................................................................. 29

Output Timing 2................................................................................................................................................................................. 30

Input Control Setup and Hold Timing ................................................................................................................................................ 30

List of Figures

June 19, 2006

IDT82V3010相似产品对比

	IDT82V3010	IDT82V3010PV	IDT82V3010PVG
描述	SPECIALTY TELECOM CIRCUIT, PDSO56	SPECIALTY TELECOM CIRCUIT, PDSO56	SPECIALTY TELECOM CIRCUIT, PDSO56
功能数量	1	1	1
端子数量	56	56	56
最小工作温度	-40 Cel	-40 Cel	-40 Cel
最大工作温度	85 Cel	85 Cel	85 Cel
加工封装描述	GREEN, SSOP-56	GREEN, SSOP-56	GREEN, SSOP-56
each_compli	Yes	Yes	Yes
欧盟RoHS规范	Yes	Yes	Yes
状态	Active	Active	Active
通信类型	TELECOM CIRCUIT	TELECOM CIRCUIT	TELECOM CIRCUIT
jesd_30_code	R-PDSO-G56	R-PDSO-G56	R-PDSO-G56
jesd_609_code	e3	e3	e3
moisture_sensitivity_level	1	1	1
包装材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
ckage_code	SSOP	SSOP	SSOP
包装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR
包装尺寸	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
eak_reflow_temperature__cel_	260	260	260
qualification_status	COMMERCIAL	COMMERCIAL	COMMERCIAL
seated_height_max	2.79 mm	2.79 mm	2.79 mm
额定供电电压	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子涂层	MATTE TIN	MATTE TIN	MATTE TIN
端子形式	GULL WING	GULL WING	GULL WING
端子间距	0.6350 mm	0.6350 mm	0.6350 mm
端子位置	DUAL	DUAL	DUAL
ime_peak_reflow_temperature_max__s_	30	30	30
length	18.42 mm	18.42 mm	18.42 mm
width	7.49 mm	7.49 mm	7.49 mm

IDT82V3010

IDT82V3010概述

IDT82V3010规格参数

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IDT82V3010相似产品对比

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