Standard Products
UT8ER512K32 Monolithic 16M SRAM
Data Sheet
June 25, 2010
www.aeroflex.com/memories
FEATURES
20ns Read, 10ns Write maximum access times
Functionally compatible with traditional 512K x 32 SRAM
devices
CMOS compatible input and output levels, three-state
bidirectional data bus
- I/O Voltage 3.3 volt, 1.8 volt core
Operational environment:
- Total-dose: 100 krad(Si)
- SEL Immune: 111MeV-cm
2
/mg
- SEU error rate = 6.0x10
-16
errors/bit-day assuming
geosynchronous orbit, Adam’s 90% worst environment,
and 6600ns default Scrub Rate Period (=97% SRAM
availability)
Packaging options:
- 68-lead ceramic quad flatpack (6.898 grams)
Standard Microcircuit Drawing 5962-06261
- QML Q & V
INTRODUCTION
The UT8ER512K32 is a high-performance CMOS static RAM
organized as 524,288 words by 32 bits. Easy memory expansion
is provided by active LOW and HIGH chip enables (E1, E2), an
active LOW output enable (G), and three-state drivers. This
device has a power-down feature that reduces power
consumption by more than 90% when deselected.
Writing to the device is accomplished by driving chip enable one
(E1) input LOW, chip enable two (E2) HIGH and write enable
(W) input LOW. Data on the 32 I/O pins (DQ0 through DQ31)
is then written into the location specified on the address pins (A0
through A18). Reading from the device is accomplished by
taking chip enable one (E1) and output enable (G) LOW while
forcing write enable (W) and chip enable two (E2) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins will appear on the I/O pins.
The 32 input/output pins (DQ0 through DQ31) are placed in a
high impedance state when the device is deselected (E1 HIGH
or E2 LOW), the outputs are disabled (G HIGH), or during a
write operation (E1 LOW, E2 HIGH and W LOW).
A0
A1
W
E1
E2
A2
A3
A4
A5
Row Select
A6
A7
A8
A9
A17
G
A18
Column Select
Memory Array
512K x 32
Pre-Charge Circuit
I/O Circuit
DQ(31) to DQ(0)
Read/Write
Circuit
Data Control
A10 A11 A12 A13 A14 A15 A16
EDAC
BUSY, SCRUB
MBE
Figure 1. UT8ER512K32 SRAM Block Diagram
1
UT8ER512K32 Master or Slave Options
To reduce the bit error rates, the UT8ER512K32 employs an
embedded EDAC (error detection and correction) with user
programmable auto scrubbing options. The UT8ER512K32
device automatically corrects single bit word errors in event of
an upset. During a read operation, if a multiple bit error occurs
in a word, the UT8ER512K32 asserts the MBE (multiple bit
error) output to notify the host.
The UT8ER512K32 is offered in two options: Master
(UT8ER512K32M) or Slave (UT8ER512K32S). The master is
a full function device which features user defined autonomous
EDAC scrubbing options. The slave device employs a scrub on
demand feature.
The UT8ER512K32M (master) and UT8ER512K32S (slave)
device pins SCRUB and BUSY are physically different. The
SCRUB pin is an output on master devices, but an input on slave
devices. The master SCRUB pin asserts low when a scrub cycle
initiates, and can be used to demand scrub cycles from multiple
slave units when connected to the SCRUB input of slave(s). The
BUSY pin is an output for the master device and can be used to
generate wait states by the memory controller. The BUSY pin
is a no connect (NC) for slave units.
PIN DESCRIPTIONS
Pins
A(18:0)
DQ(31:0)
E1
E2
W
G
V
DD1
V
DD2
V
SS
MBE
SCRUB
SCRUB
BUSY
BUSY
Type
I
BI
I
I
I
I
P
P
P
BI
I
O
NC
O
Description
Address
Data Input/Output
Enable (Active Low)
Enable (Active High)
Write Enable
Output Enable
Power (1.8)
Power (3.3V)
Ground
Multiple Bit Error
Slave SCRUB Input
Master SCRUB Output
Slave No Connect
Master Wait State Control
DEVICE OPERATION
The UT8ER512K32 has four control inputs called Enable 1
(E1), Enable 2 (E2), Write Enable (W), and Output Enable (G);
19 address inputs, A(18:0); and 32 bidirectional data lines,
DQ(31:0). E1 and E2 device enables control device selection,
active, and standby modes. Asserting E1 and E2 enables the
device, causes I
DD
to rise to its active value, and decodes the 19
address inputs to select one of 524,288 words in the memory. W
controls read and write operations. During a read cycle, G must
be asserted to enable the outputs.
Table 1. SRAM Device Control Operation Truth Table
G
X
X
L
H
Note:
Pin 31 on the UT8ER512K32S (Slave) is a no connect (NC).
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
V
SS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
1
2
3
4
5
Top View
6
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCRUB
W
A6
A7
A8
A9
A10
V
DD1
V
SS
A0
A1
A2
A3
A4
A5
V
SS
A17
A18
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
W
X
X
H
H
L
E2
X
L
H
H
H
E1
H
X
L
L
L
I/O Mode
DQ(31:0)
3-State
DQ(31:0)
3-State
DQ(31:0)
Data Out
DQ(31:0)
All 3-State
DQ(31:0)
Data In
Mode
Standby
Standby
Word Read
Word Read
2
Word Write
V
DD1
A11
A12
A13
A14
A15
A16
E1
G
E2
V
DD2
V
SS
Figure 2. 20ns SRAM Pinout (68)
Busy
MBE
V
DD2
V
SS
X
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
2
Table 2. EDAC Control Pin Operation Truth Table
MBE
H
L
X
X
SCRUB
H
H
H
H
BUSY
H
H
H
L
I/O Mode
Read
Read
X
X
Mode
Uncorrectable
Multiple Bit Error
Valid Data Out
Device Ready
Device Ready /
Scrub Request
Pending
Device Busy
WRITE CYCLE
A combination of W and E1 less than V
IL
(max), and E2 greater
than V
IH
(min) defines a write cycle. The state of G is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either G is greater than V
IH
(min), or when
W is less than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access in Figure 4a,
is defined by a write terminated by W going high, with E1 and
E2 still active. The write pulse width is defined by t
WLWH
when
the write is initiated by W, and by t
ETWH
when the write is
initiated by E1 and E2. To avoid bus contention t
WLQZ
must be
satisfied before data is applied to the 32 bidirectional pins
DQ(31:0) unless the outputs have been previously placed in high
impedance state by deasserting G.
Write Cycle 2, the Chip Enable-controlled Access in Figure 4b,
is defined by a write terminated by the latter of E1 or E2 going
inactive. The write pulse width is defined by t
WLEF
when the
write is initiated by W, and by t
ETEF
when the write is initiated
by either E1or E2 going active. For the W initiated write, unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait t
WLQZ
before applying data to the
thirty-two bidirectional pins DQ(31:0) to avoid bus contention.
CONTROL REGISTER WRITE/READ CYCLES
Configuration options can be selected by writing to the control
register. The configuration table (Table 4) details the
programming options. The control register is accessed by
applying a series of values to the address bus as shown in Figure
6a. The contents of the control register are written following the
fifth address. The contents of the address bus are written to the
control register if bit 9 is zero. The contents of the control register
are output to the data bus if bit 9 is one.
NOTE:
MBE must be
driven high by the user for both a write or a read of the control
register.
MEMORY SCRUBBING/CYCLE STEALING
The UT8ER512K32 SRAM uses architectural improvements
and embedded error detection and correction to maintain
unsurpassed levels of error protection. This is accomplished by
what Aeroflex refers to as Cycle Stealing. To minimize the
system design impact on the speed of operation, the edge
relationship between BUSY and SCRUB is programmable via
the sequence described in figure 6a.
The effective error rate is a function of the intrinsic rate and the
environment. As a result, some users may desire an increased
scrub rate to lower the error rate at the sacrifice of reduced total
throughput, while others may desire a lower scrub rate to
X
L
X
Not
Accessible
Notes:
1. “X” is defined as a “don’t care” condition
2. Busy signal is a "NC" for UT8ER512K32S slave device and is an "X" don’t
care.
READ CYCLE
A combination of W and E2 greater than V
IH
(min) and E1 and
G less than V
IL
(max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access in Figure 3a, is
initiated by a change in address inputs while E1 and E2 are
asserted, G is asserted, and W is deasserted. Valid data appears
on data outputs DQ(31:0) after the specified t
AVQV
is satisfied.
Outputs remain active throughout the entire cycle. As long as
device enable and output enable are active, the minimum time
between valid address changes is specified by the read cycle
time (t
AVAV
).
SRAM Read Cycle 2, the Chip Enable-controlled Access in
Figure 3b, is initiated by the latter of either E1and E2 going
active while G remains asserted, W remains deasserted, and the
addresses remain stable for the entire cycle. After the specified
t
ETQV
is satisfied, the 32-bit word addressed by A(18:0) is
accessed and appears at the data outputs DQ(31:0).
SRAM Read Cycle 3, the Output Enable-controlled Access in
Figure 3c, is initiated by G going active while E1 and E2 are
asserted, W is deasserted, and the addresses are stable. Read
access time is t
GLQV
unless t
AVQV
or t
ETQV
(reference Figure
3b) have not been satisfied.
SRAM EDAC Status Indications during a Read Cycle, if MBE
is Low, the data is good. If MBE is High the data is corrupted
(reference Table 2).
3
increase the total throughput and accept a higher error rate. This
rate at which the SRAM controller will correct errors from the
memory is user programmable. The required sequence is
described in figure 6a.
A master mode scrub cycle will occur at the user defined Scrub
Rate Period. A scrub cycle is defined as the verification and
correction (if necessary) of data for a single word address
location. Address locations are scrubbed sequentially every
Scrub Rate Period (t
SCRT
). Scrub cycles will occur at every
Scrub Rate Period regardless of the status of control pins.
Control pin function will be returned upon deassertion of BUSY
pin. The Slave mode scrub cycle occurs anytime the SCRUB
pin is asserted. The scrub cycle is defined the same as the master
mode, and will occur regardless of control pin status. Control
pin function will be returned upon SCRUB deassertion.
Data is not only corrected during the internal scrub, but again
during a user requested read cycle. If the data presented con-
tains two or more errors after t
AVAV
is satisfied, the MBE signal
will be asserted. (Note: Reading un-initialized memory
locations may result in un-intended MBE assertions.)
Operational Environment
The UT8ER512K32 SRAM incorporates special design, layout,
and process features which allows operation in a limited
environment.
Table 3. Operational Environment Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
100K
6.0x10
-16
rad(Si)
Errors/Bit-Day
Notes:
1. The SRAM is immune to latchup to particles >111MeV-cm
2
/mg.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum and default EDAC scrub rate.
SUPPLY SEQUENCING
No supply voltage sequencing is required between V
DD1
and
V
DD2
.
POWER-UP REQUIREMENTS
During power-up of the UT8ER512K32 device, the power
supply voltages will transverse through voltage ranges where
the device is not guaranteed to operate before reaching final
levels. Since some circuits on the device will start to operate at
lower voltage levels than others, the device may power-up in an
unknown state. To eliminate this with most power-up situations,
the device employs an on-chip power-on-reset (POR) circuit.
The POR, however, requires time to complete the operation.
Therefore, it is recommended that all device activity be delayed
by a minimum of 100ms, after both V
DD1
and V
DD2
supplies
have reached their respective minimum operating voltage.
4
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD1
V
DD2
V
I/O
T
STG
P
D2
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage (Core)
DC supply voltage (I/O)
Voltage on any pin
Storage temperature
Maximum package power dissipation
permitted @ Tc = +125
o
C
Maximum junction temperature
Thermal resistance, junction-to-case
2
DC input current
LIMITS
-0.3 to 2.1V
-0.3 to 3.8V
-0.3 to 3.8V
-65 to +150°C
5W
+150°C
5°C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Per MIL-STD-883, Method 1012, Section 3.4.1, P
D
= (T
JC
(max) - Tc (max))
Θ
JC
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD1
V
DD2
T
C
V
IN
PARAMETER
DC supply voltage (Core)
DC supply voltage (I/O)
Case temperature range
DC input voltage
LIMITS
1.7 to 1.9V
1
3.0 to 3.6V
(C) Screening: -55 to +125°C
(W) Screening: -40 to +125°C
0V to V
DD2
Notes:
1. For increased noise immunity, supply voltage V
DD1
can be increased to 2.0V. All characteristics contained herein are guaranteed by characterization at V
DD1
= 2.0Vdc unless otherwise specified.
5
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