WS512K32-XXX
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
Access Times of 15, 17, 20, 25, 35, 45, 55ns
Packaging
• 66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400).
• 68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm
(0.140") (Package 502)
1
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880") square
(Package 510) 3.56mm (0.140") height.
• 68 lead, Hermetic CQFP (G2L), 22.4mm (0.880") square,
5.08mm (0.200") high (Package 528).
Organized as 512Kx32, User Configurable as 1Mx16 or
2Mx8
Commercial, Industrial and Military Temperature Ranges
TTL Compatible Inputs and Outputs
5 Volt Power Supply
Low Power CMOS
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
Weight
WS512K32N-XH1X - 13 grams typical
WS512K32-XG2UX - 8 grams typical
WS512K32-XG4TX
1
- 20 grams typical
WS512K32-XG2LX - 8 grams typical
* This product is subject to change without notice.
Note 1: Package Not Recommended For New Design
FIGURE 1 – PIN CONFIGURATION FOR WS512K32N-XH1X
Top View
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
18
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
66
512K X 8
OE#
A
0-18
WE
1
# CS
1
#
Pin Description
56
I/O
0-31
A
0-18
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
512K X 8
512K X 8
512K X 8
8
8
8
8
I/O
0 - 7
I/O
8 - 15
I/O
16 - 23
I/O
24 - 31
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2016
Rev. 22
© 2016 Microsemi Corporation. All rights reserved.
1
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WS512K32-XXX
FIGURE 2 – PIN CONFIGURATION FOR WS512K32-XG4TX
1
Top View
I/O
0-31
A
0-18
WE#
CS
1-4
#
OE#
V
CC
GND
NC
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Block Diagram
WE#
OE#
A
0-18
CS
1
#
CS
2
#
CS
3
#
CS
4
#
512K X 8
512K X 8
512K X 8
512K X 8
A
15
A
16
CS
1
#
OE#
V
CC
A
11
A
12
A
13
A
14
A
17
NC
NC
NC
A
18
CS
2
#
NC
NC
8
8
8
8
I/O
0 - 7
I/O
8 - 15
I/O
16 - 23
I/O
24 - 31
Note 1: Package Not Recommended For New Design
FIGURE 3 – PIN CONFIGURATION FOR WS512K32-XG2UX AND WS512K32-XG2LX
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
I/O
0-31
A
0-18
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
A
17
WE
2
#
WE
3
#
WE
4
#
A
18
NC
NC
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Block Diagram
WE
1
# CS
1
#
OE#
A
0-18
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
512K X 8
512K X 8
512K X 8
512K X 8
8
8
8
8
I/O
0 - 7
I/O
8 - 15
I/O
16 - 23
I/O
24 - 31
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2016
Rev. 22
© 2016 Microsemi Corporation. All rights reserved.
2
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WS512K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
H
X
TRUTH TABLE
WE
X
H
H
L
Mode
Standby
Read
Out Disable
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
CAPACITANCE
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.5
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Parameter
OE# capacitance
WE
1-4
# capacitance
HIP (PGA)
CQFP G4T
CQFP G2U/G2L
CS
1-4
# capacitance
Data I/O capacitance
Address input capacitance
Ta = +25°C
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
Max Unit
50
pF
pF
20
50
20
20
pF
20
pF
50
pF
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current x 32 Mode
Standby Current
Output Low Voltage
Output High Voltage
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
Symbol
I
LI
I
LO
I
CC
x 32
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 6mA for 15 - 35ns,
I
OL
= 2.1mA for 45 - 55ns, V
CC
= 4.5
I
OH
= -4.0mA for 15 - 35ns,
I
OH
= -1.0mA for 45 - 55ns, V
CC
= 4.5
Min
Max
10
10
660
80
0.4
Units
μA
μA
mA
mA
V
V
2.4
DATA RETENTION CHARACTERISTICS
(Ta = -55°C to +125°C)
Parameter
Data Retention Supply Voltage
Data Retention Current
Low Power Data Retention Current (WS512K32L-XXX)
Symbol
V
DR
I
CCDR1
I
CCDR2
Conditions
CS
≥
V
CC
−
0.2V
V
CC
= 3V
V
CC
= 3V
Min
2.0
Max
5.5
28
16
Units
V
mA
mA
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2016
Rev. 22
© 2016 Microsemi Corporation. All rights reserved.
3
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WS512K32-XXX
AC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
-15
Min Max
15
15
0
15
8
2
0
12
12
-17
Min Max
17
17
0
17
9
2
0
12
12
-20
Min Max
20
20
0
20
10
2
0
12
12
-25
Min Max
25
25
0
25
12
2
0
12
12
-35
Min Max
35
35
0
35
25
4
0
15
15
-45
Min Max
45
45
0
45
25
4
0
20
20
-55
Min Max Units
55
ns
55
ns
0
ns
55
ns
25
ns
4
ns
0
ns
20
ns
20
ns
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
-15
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
Min
15
13
13
10
13
2
0
2
0
Max
Min
17
15
15
11
15
2
0
2
0
-17
Max
Min
20
15
15
12
15
2
0
3
0
-20
Max
Min
25
17
17
13
17
2
0
4
0
-25
Max
Min
35
25
25
20
25
2
0
4
0
-35
Max
Min
45
35
35
25
35
2
5
5
0
-45
Max
Min
55
50
50
25
40
2
5
5
0
-55
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
9
11
13
15
20
20
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2U, G1U and H1 packages. t
AS
minimum for the G4T package is 0ns.
FIGURE. 4 – AC TEST CIRCUIT
AC Test Conditions
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
V
Z
≈ 1.5V
(Bipolar Supply)
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
Current Source
I
OH
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2016
Rev. 22
© 2016 Microsemi Corporation. All rights reserved.
4
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
WS512K32-XXX
FIGURE 5 – TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 2, (CS# = OE# = V
IL
, WE# = V
IH
)
READ CYCLE 2 (WE# = V
IH
)
FIGURE 6 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
FIGURE 7 – WRITE CYCLE - CS# CONTROLLED
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
Microsemi Corporation reserves the right to change products or specifications without notice.
April 2016
Rev. 22
© 2016 Microsemi Corporation. All rights reserved.
5
Microsemi Corporation • (602) 437-1520 • www.microsemi.com/pmgp
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