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IDT74SSTU32864DBFG: 产品描述D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, GREEN, LFBGA-96; 产品类别逻辑; 文件大小181KB，共12页; 制造商IDT (Integrated Device Technology); 标准

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IDT74SSTU32864DBFG概述

D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, GREEN, LFBGA-96

IDT74SSTU32864DBFG规格参数

参数名称	属性值
是否Rohs认证	符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	LFBGA, BGA96,6X16,32
针数	96
Reach Compliance Code	unknown
其他特性	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE
系列	SSTU
JESD-30 代码	R-PBGA-B96
JESD-609代码	e1
长度	13.5 mm
逻辑集成电路类型	D FLIP-FLOP
湿度敏感等级	3
位数	25
功能数量	1
端子数量	96
最高工作温度	70 °C
最低工作温度
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	LFBGA
封装等效代码	BGA96,6X16,32
封装形状	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260
电源	1.8 V
传播延迟（tpd）	2.35 ns
认证状态	Not Qualified
座面最大高度	1.5 mm
最大供电电压 (Vsup)	1.9 V
最小供电电压 (Vsup)	1.7 V
标称供电电压 (Vsup)	1.8 V
表面贴装	YES
温度等级	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL
端子节距	0.8 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	30
触发器类型	POSITIVE EDGE
宽度	5.5 mm
最小 fmax	340 MHz
Base Number Matches	1

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IDT74SSTU32864/A/C/D/G

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

COMMERCIAL TEMPERATURE RANGE

1:1 AND 1:2 REGISTERED

BUFFER WITH 1.8V SSTL I/O

IDT74SSTU32864/

A/C/D/G

FEATURES:

•

1:1 and 1:2 registered buffer

1.8V Operation

SSTL_18 style clock and data inputs

Differential CLK input

Control inputs compatible with LVCMOS levels

Flow-through architecture for optimum PCB design

Latch-up performance exceeds 100mA

ESD >2000V per MIL-STD-883, Method 3015; >200V using

machine model (C = 200pF, R = 0)

• Maximum operating frequency: 340MHz

• Available in 96-pin LFBGA package

APPLICATIONS:

• Ideally suited for DDR2-400/533 (PC2 - 3200/ 4200) registered

DIMM applications

• Along with CSPU877/A/D, zero delay PLL clock buffer, provides

complete solution for DDR2-400/533 DIMMs

• SSTU32864 is optimized for DDR2 Raw cards B and C

• SSTU32864A is optimized for DDR2 Raw card A

• SSTU32864C/D/G are optimized for DDR2 Raw cards A, B, and C

• SSTU32864G has control pins for output slew rate control

The SSTU32864 is a 25-bit 1:1 / 14-bit 1:2 configurable registered buffer

designed for 1.7V to 1.9V V

operation. All clock and data inputs are

compatible with the JEDEC standard for SSTL_18. The control inputs are

LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized

to drive the DDR2 DIMM load.

The SSTU32864 operates from a differential clock (CLK and

CLK).

Data

are registered at the crossing of CLK going high and

CLK

going low.

The C0 input controls the pinout configuration of the 1:2 pinout from the

A configuration (when low) to B configuration (when high). The C1 input

controls the configuration from the 25-bit 1:1 (when low) to 14-bit 1:2 (when

high).

This device supports low-power standby operation. When the reset input

(RESET) is low, the differential input receivers are disabled, and undriven

(floating) data, clock, and reference voltage (V

REF

) inputs are allowed. In

addition, when

RESET

is low all registers are reset, and all outputs are

forced low. The LVCMOS

RESET

and Cx inputs must always be held at

a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has

been supplied,

RESET

must be held in the low state during power up.

In the DDR2 DIMM application,

RESET

is specified to be completely

asynchronous with respect to CLK and

CLK.

Therefore, no timing

relationship can be guaranteed between the two. When entering reset, the

to the time to disable the differential input receivers. However, when coming

out of a reset, the register will become active quickly, relative to the time to

enable the differential input receivers. As long as the data inputs are low,

and the clock is stable during the time from the low-to-high transition of

RESET

until the input receivers are fully enabled, the design of the

SSTU32864 must ensure that the outputs will remain low, thus ensuring no

glitches on the outputs.

The device monitors both DCS and

CSR

inputs and will gate the outputs

from changing states when both DCS and

CSR

inputs are high. If either

DCS or

CSR

input is low, the device will function normally. The

RESET

input has priority over the DCS control and will force the inputs low. If the

DCS control functionality is not desired, then the

CSR

input can be hard-

wired to ground, in which case the set-up time requirement for DCS would

be the same as for the other D data inputs.

The SSTU32864G has two slew control pins (Z

and Z

) used to

optimize the signal integrity on the DIMM.

DESCRIPTION:

COMMERCIAL TEMPERATURE RANGE

2006 Integrated Device Technology, Inc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

APRIL 2006

DSC-5980/27

IDT74SSTU32864DBFG相似产品对比

	IDT74SSTU32864DBFG	IDT74SSTU32864DBFG8	IDT74SSTU32864ABFG8	IDT74SSTU32864ABFG
描述	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, GREEN, LFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, GREEN, LFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, GREEN, LFBGA-96	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, PBGA96, GREEN, LFBGA-96
是否Rohs认证	符合	符合	符合	符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	BGA	BGA	BGA	BGA
包装说明	LFBGA, BGA96,6X16,32	LFBGA, BGA96,6X16,32	LFBGA, BGA96,6X16,32	LFBGA, BGA96,6X16,32
针数	96	96	96	96
Reach Compliance Code	unknown	unknown	unknown	unknown
其他特性	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE	14 BIT 1:2 CONFIGURATION ALSO POSSIBLE
系列	SSTU	SSTU	SSTU	SSTU
JESD-30 代码	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96	R-PBGA-B96
JESD-609代码	e1	e1	e1	e1
长度	13.5 mm	13.5 mm	13.5 mm	13.5 mm
逻辑集成电路类型	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP	D FLIP-FLOP
湿度敏感等级	3	3	3	3
位数	25	25	25	25
功能数量	1	1	1	1
端子数量	96	96	96	96
最高工作温度	70 °C	70 °C	70 °C	70 °C
输出极性	TRUE	TRUE	TRUE	TRUE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFBGA	LFBGA	LFBGA	LFBGA
封装等效代码	BGA96,6X16,32	BGA96,6X16,32	BGA96,6X16,32	BGA96,6X16,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260	260	260	260
电源	1.8 V	1.8 V	1.8 V	1.8 V
传播延迟（tpd）	2.35 ns	2.35 ns	2.35 ns	2.35 ns
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.5 mm	1.5 mm	1.5 mm	1.5 mm
最大供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	30	30	30	30
触发器类型	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
宽度	5.5 mm	5.5 mm	5.5 mm	5.5 mm
最小 fmax	340 MHz	340 MHz	340 MHz	340 MHz
Base Number Matches	1	1	1	1

IDT74SSTU32864DBFG

IDT74SSTU32864DBFG概述

IDT74SSTU32864DBFG规格参数

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