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74AUP1G125GM-H

产品描述IC AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6, 1 X 1.45 MM, 0.5 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Bus Driver/Transceiver
产品类别逻辑   
文件大小105KB,共21页
制造商NXP(恩智浦)
官网地址https://www.nxp.com
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74AUP1G125GM-H概述

IC AUP/ULP/V SERIES, 1-BIT DRIVER, TRUE OUTPUT, PDSO6, 1 X 1.45 MM, 0.5 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Bus Driver/Transceiver

74AUP1G125GM-H规格参数

参数名称属性值
厂商名称NXP(恩智浦)
零件包装代码SON
包装说明VSON,
针数6
Reach Compliance Codeunknown
系列AUP/ULP/V
JESD-30 代码R-PDSO-N6
长度1.45 mm
逻辑集成电路类型BUS DRIVER
位数1
功能数量1
端口数量2
端子数量6
最高工作温度125 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码VSON
封装形状RECTANGULAR
封装形式SMALL OUTLINE, VERY THIN PROFILE
传播延迟(tpd)24 ns
认证状态Not Qualified
座面最大高度0.5 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)0.8 V
标称供电电压 (Vsup)1.8 V
表面贴装YES
技术CMOS
温度等级AUTOMOTIVE
端子形式NO LEAD
端子节距0.5 mm
端子位置DUAL
宽度1 mm
Base Number Matches1

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74AUP1G125
Low-power buffer/line driver; 3-state
Rev. 02 — 30 June 2006
Product data sheet
1. General description
The 74AUP1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all
inputs makes the circuit tolerant to slower input rise and fall times across the entire
V
CC
range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power
consumption across the entire V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G125 provides the single non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (OE).
A HIGH level at pin OE causes the output to assume a high-impedance OFF-state. This
device has the input-disable feature, which allows floating input signals. The inputs are
disabled when OE is HIGH.
2. Features
I
Wide supply voltage range from 0.8 V to 3.6 V
I
High noise immunity
I
Complies with JEDEC standards:
N
JESD8-12 (0.8 V to 1.3 V)
N
JESD8-11 (0.9 V to 1.65 V)
N
JESD8-7 (1.2 V to 1.95 V)
N
JESD8-5 (1.8 V to 2.7 V)
N
JESD8-B (2.7 V to 3.6 V)
I
ESD protection:
N
HBM JESD22-A114-C Class 3A. Exceeds 5000 V
N
MM JESD22-A115-A exceeds 200 V
N
CDM JESD22-C101-C exceeds 1000 V
I
Low static power consumption; I
CC
= 0.9
µA
(maximum)
I
Latch-up performance exceeds 100 mA per JESD 78 Class II
I
Inputs accept voltages up to 3.6 V
I
Low noise overshoot and undershoot < 10 % of V
CC
I
Input-disable feature allows floating input conditions
I
I
OFF
circuitry provides partial Power-down mode operation
I
Multiple package options
I
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C

 
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