The IDT80KSBR200 is a high speed Serial Buffer (SerB) that can
connect to any Serial RapidIO compliant interface. This device is built to
work with any sRIO device and especially with the IDT Pre-Processing
Switch (PPS), IDT70K200. The SerB performs buffering and off-loading
of data as well as buffer-delay of data samples in various environments.
This device primarily acts as an master in which the SerB bursts data to
a programmed memory location once some criteria have been meet.
This combination of storage and flexibility make it the perfect buffering
solution for sRIO systems.
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Programmable Target Address
Packet Tally Indicator
Packet Interval Timer
Replace Missing Packet
Optional External QDR SRAM Available
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–
–
–
–
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Up to 72Mbit external QDR SRAM
QDR SRAM, 200 MHz; (18M, 36M, 72M)
Internal and external memory functions as a single buffer
Seamless Integration of Internal and External Memory
Single Port Buffering
Status Flags for Combined Internal/External Memories
Full, Empty, Partially Empty, Partially Full
Features
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Direct or polled operation of flag status bus
Optional Watermark
Interface - I
2
C Interface Port
Serial Buffer can Either Send a Flag or Transmit Data at a Specific Packet
Count
One I
2
C port for maintenance and error reporting
JTAG Functionality for boundary scan and programming
1.2V Core operation with 3.3/2.5V JTAG interface
23mm x 23mm, 1.0mm ball pitch
Serial RapidIO Port
Interface - sRIO
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–
–
–
–
–
–
–
–
–
–
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One four-lane (4x) link, configurable to one-lane (1x) link
Port Speeds selectable: 3.125 Gbps, 2.5 Gbps, or 1.25 Gbps
Short haul or long haul reach for each PHY speed
Support 8-bit and 16-bit deviceID
Error management supports standard
sRIO version 1.3
Class 1+ End Point Device
Interface - JTAG Interface
High-Speed CMOS Technology
Package: 484-pin Plastic Ball Grid Array
10 Gbps Throughput
18Mbit Internal Density
Block Diagram
S-Port 1
Input
Deserializer
S-Port 1 Command Interpreter
MUX 10
1x/4x sRIO
Interface
Output
Serializer
Queue 0
18 Mbits
TCK
TMS
TDI
TDO
SCL
SDA
MR
FR
JTAG
Configuration
and
Flag Registers
I
2
C
MUX 3
2
PHY Clk
QDR Clk
Flags
32+4 bit Parallel
8
2
Flag Request
Flag Clk
Flag Bus
Interrupt
32+4 bit Parallel
2
2
P-Port
drw01 DSC-6730
Hardwire
Config
K/K
CQ
CQ D
Q
A Rd Wr
1 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT
AN OFFER FOR SALE
The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
2 of 172
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT
AN OFFER FOR SALE
The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
Table of Contents
1.0 Functional Description
Interface Overview
9
10
2.0 Applications
PPS Data Storage
Compatible External Memory
13
13
13
3.0 Protocols
SerB Packet Characteristics
sRIO Specification
sRIO Simplified Overview
The sRIO Packet
The sRIO Control Symbols
Use of CRC and CRC Errors
Parallel Port Interface
15
15
15
17
18
24
24
24
4.0 Data Handling
Inputting Data to the Queues
Outputting Data from the Queues
Use of Acknowledgements
Idles
Case Scenarios
Water Levels and Watermarks
Missing Packet Detection and Replacement
Packet Tally Indicator
Packet Interval Timer
Protocol Translation
25
25
25
26
27
27
28
29
31
31
31
5.0 Doorbells and Interrupts
Doorbell Characteristics
External Interrupt Pins
33
33
34
6.0 Device Programming
Vendor IDs
Memory Map
Programming and Reset
35
35
35
37
7.0 Error Management
sRIO Errors and Error Handling
System Software Error Notification
sRIO Errors Supported
Other SerB Errors
41
41
41
42
61
8.0 Registers
sRIO Registers
Configuration Registers
SerB Error Counter Registers
Serdes Quad Control Registers
Flag and Flag Mask Registers
63
63
88
100
102
102
9.0 Reset and Initialization
Speed Select
sRIO Reset Control Symbol
JTAG Reset
System Initialization
Initialization of RIO Ports
111
111
111
111
111
112
10.0 Reference Clock
Reference Clock Electrical Specifications
113
113
11.0 Absolute Maximum Ratings
3 of 172
114
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT
AN OFFER FOR SALE
The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT
AN OFFER FOR SALE
The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
IDT 80KSBR200
Advanced Datasheet*
Notes
List of Tables
Table 1: SerB Memory Map
Table 2: Port-write Packet Data Payload for Error Reporting
Table 3: Physical RIO Errors Detected
Table 4: Physical RIO Threshold Response
Table 5: Hardware Errors for NRead Transaction
Table 6: Hardware Errors for Maintenance Read/Write Request Transaction
Table 7: Hardware Errors for RIO Write Class Transactions
Table 8: Hardware Errors for SWrite Class Transactions
Table 9: Hardware Errors for Maintenance Response Transactions
Table 10: Hardware Errors for Response Transactions
Table 11: Hardware Errors for Reserved FType
Table 12: RIO Base Feature Address Space
Table 13: Device ID CAR
Table 14: Device Information CAR
Table 15: Assembly ID CAR
Table 16: Assembly Info CAR
Table 17: Process Element Features CAR
Table 18: Source Operations CAR
Table 19: Destination Operations CAR
Table 20: Processing Element Logical Layer Control CSR
Table 21: Local Configuration Space Base Address 1 CSR
Table 39: Logical/Transport Layer Device ID Capture CSR
Table 40: Logical/Transport Layer Control Capture CSR
Table 41: Port-write Target Device ID CSR
Table 42: Port 0 Error Detect CSR
Table 43: Port 0 Error Rate Enable CSR
Table 44: Port 0 Attribute Capture CSR
Table 45: Port 0 Packet/Control Symbol Capture 0 CSR
Table 46: Port 0 Packet/Control Symbol Capture 1 CSR
Table 47: Port 0 Packet/Control Symbol Capture 2 CSR
Table 48: Port 0 Packet/Control Symbol Capture 3 CSR
Table 49: Port 0 Error Rate CSR
Table 50: Port 0 Error Rate Threshold CSR
Table 51: Reset and Command Register
Table 52: Serial Port Configuration Register
Table 53: Parallel Port Configuration Register
Table 54: Memory Allocation Register
5 of 172
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67
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70
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79
81
81
82
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86
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86
87
88
89
90
90
90
March 19, 2007
„2005 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice.NOT
AN OFFER FOR SALE
The information presented herein is subject to a
Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance.
Microchip MCU
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